--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity DIST is
	port(rst : in STD_LOGIC;
	     clk : in STD_LOGIC;
	     start : in STD_LOGIC;
	     x : in UNSIGNED (7 downto 0);
	     y : in UNSIGNED (7 downto 0);
	     d : out UNSIGNED (3 downto 0);
	     done : out STD_LOGIC);
end DIST;

--**************************************************************************--

architecture BHV_DIST of DIST is

	type STATE_TYPE is (S0, S1, S2);

	constant C0_4 : UNSIGNED (3 downto 0) := "0000";
	constant C1_4 : UNSIGNED (3 downto 0) := "0001";
	constant C8_4 : UNSIGNED (3 downto 0) := "1000"

	signal state : STATE_TYPE;
	signal i, j : UNSIGNED (3 downto 0);
begin
	process(rst, clk)
	begin
		if( rst = '1' ) then

			--
			-- reset
			-- 
			state <= S0;
			i <= C0_4;
			j <= C0_4;
			d <= C0_4;
			done <= '0';

		elsif( clk'event and clk = '1' ) then

			--
			-- FSMD
			--
			case state is
				when S0 =>
					if( start = '1' ) then

						state <= S1;
						i <= C0_4;
						j <= C0_4;
						d <= C0_4;
						done <= '0';
					end if;

				when S1 =>
					if( i = C8_4 ) then 

						state <= S2;
					else

						state <= S1;
						if( x(conv_integer(i)) /= 
						    y(conv_integer(i)) ) then

							j <= j + C1_4;
						end if;
						i <= i + C1_4;
					end if;

				when S2 =>
					state <= S0;
					d <= j;
					done <= '1';
			end case;
		end if;
	end process;
end BHV_DIST;

--**************************************************************************--

configuration CFG_DIST of DIST is
   for BHV_DIST
   end for;
end CFG_DIST;


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