library ieee;
use ieee.std_logic_1164.all;
-- 4 to 1 mux, 8 bit inputs, using sequential statement
entity mux4to1_8_seq is
port (
I0,I1,I2,I3 : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(7 downto 0)
);
end mux4to1_8_seq;
architecture a of mux4to1_8_seq is
begin
process (sel,I0, I1, I2, I3)
begin
CASE sel IS
WHEN "00" => dout <= I0;
WHEN "01" => dout <= I1;
WHEN "10" => dout <= I2;
WHEN others => dout <= I3;
end case;
end process;
end a;
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