-------------------------------------------------------------------------------
-- EE 126 Project # 1, Serial Arithmetic and Logic Unit, part 1
-- VHDL implementation by: Frank Bruno
-- Part of a project for Professor Chang
-------------------------------------------------------------------------------
ENTITY alu_1 IS
PORT(opcode : IN bit_vector(2 DOWNTO 0);
a : IN bit;
b : IN bit;
cin : IN bit;
clock : IN bit;
s : OUT bit;
cout : OUT bit);
END alu_1;
ARCHITECTURE behave_alu_1 OF alu_1 IS
BEGIN -- behave
PROCESS
BEGIN
WAIT UNTIL clock'EVENT and clock='1';
CASE opcode IS
WHEN "000" => -- clear, s <= 0
s <= '0';
WHEN "001" => -- compliment, s <= a'
s <= NOT(a);
WHEN "010" => -- increment, s <= a+cin
s <= a XOR cin;
cout <= a AND cin;
WHEN "011" => -- negate, s <= a' + cin
s <= NOT(a XOR cin);
cout <= (NOT(a)) AND cin;
WHEN "100" => -- transfer b, s <= b
s <= b;
WHEN "101" => -- XOR, a XOR b
s <= a XOR b;
WHEN "110" => -- Add, a + b + cin
s <= (a XOR b) XOR cin;
cout <= (a AND cin) OR (b AND (a XOR cin));
WHEN "111" => -- Subtract, a + b' + cin
s <= a XOR (NOT(b)) XOR cin;
cout <= (a AND cin) OR ((NOT(b)) AND (a XOR cin));
WHEN OTHERS =>
END CASE; -- opcode
END PROCESS;
END behave_alu_1;
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