use STD.TEXTIO.all;

entity Read_in is
  port(RX, RY: out BIT_VECTOR(31 downto 0);
       RCIN: out BIT);
end Read_in;

architecture Read_in_arch of Read_in is
file Test_in: TEXT is "test.in";
begin

process
variable L : Line;
variable VX : Bit_vector(31 downto 0);
variable VY : Bit_vector(31 downto 0);
variable VCIN : Bit;
begin
while (not(Endfile(Test_in))) loop
  Readline(Test_in, L);
  Read(L, VX);
  Read(L, VY);
  Read(L, VCIN);
  RX <=  VX;
  RY <=  VY;
  RCIN <= VCIN;
  wait for 33 fs;
end loop;
wait;
end process;

end Read_in_arch;

use STD.TEXTIO.all;

entity Write_out is
  port(RX, RY: in BIT_VECTOR(31 downto 0);
       RCIN: in BIT;
       RSUM: in BIT_VECTOR(31 downto 0);
       RCOUT: in BIT);
end write_out;

architecture write_out_arch of write_out is
file Test_out: TEXT is "test.out";
begin

process
variable L : Line;
variable S: string(1 to 2) := "  ";
begin
  wait on RX'quiet, RY'QUIET, RCIN'quiet;
  wait for 33 fs;
  WRITE (L, Now);
  WRITE (L, S);
  WRITE (L, RX);
  WRITE (L, S);
  WRITE (L, RY);
  WRITE (L, S);
  WRITE (L, RCIN);
  WRITE (L, S);
  WRITE (L, RCOUT);
  WRITE (L, S);
  WRITE (L, RSUM);
  WRITELINE(Test_out, L);
end process;

end write_out_arch;

entity XOR2 is
  port(IN1, IN2: in BIT; OUT1: out BIT);
end XOR2;

architecture behavioral of XOR2 is
begin
  OUT1 <= IN1 xor IN2 after 1 fs;
end behavioral;


entity AND2 is
  port(IN1, IN2: in BIT; OUT1: out BIT);
end AND2;

architecture behavioral of AND2 is
begin
  OUT1 <= IN1 and IN2 after 1 fs;
end behavioral;


entity OR2 is
  port(IN1, IN2: in BIT; OUT1: out BIT);
end OR2;

architecture behavioral of OR2 is
begin
  OUT1 <= IN1 or IN2 after 1 fs;
end behavioral;


entity Full_Adder is
  port(X, Y: in BIT;
       CIN: in BIT;
       SUM: out BIT;
       COUT: out BIT);
end Full_Adder;

architecture STRUCTURAL of FULL_ADDER is
component XOR2 
  port (I1, I2: in BIT; O1: out BIT); 
end component;
component AND2 
  port (I1, I2: in BIT; O1: out BIT); 
end component;
component OR2 
  port (I1, I2: in BIT; O1: out BIT); 
end component;
signal P, G, PC: BIT; 
for all: XOR2 use entity Work.XOR2(behavioral)
  port map (IN1 => I1, IN2 => I2, OUT1 => O1);
for all: AND2 use entity Work.AND2(behavioral)
  port map (IN1 => I1, IN2 => I2, OUT1 => O1);
for all: OR2 use entity Work.OR2(behavioral)
  port map (IN1 => I1, IN2 => I2, OUT1 => O1);
begin
	U0: XOR2 port map(I1 => X, I2 => Y, O1 => P);
	U1: XOR2 port map(I1 => P, I2 => CIN, O1 => SUM);
	U2: AND2 port map(I1 => X, I2 => Y, O1 => G);
	U3: AND2 port map(I1 => P, I2 => CIN, O1 => PC);
	U4: OR2 port map(I1 => PC, I2 => G, O1 => COUT);
end STRUCTURAL;

entity thirtytwo_bit_adder is
  port(EX, EY: in BIT_VECTOR(31 downto 0);
       ECIN: in BIT;
       ESUM: out BIT_VECTOR(31 downto 0);
       ECOUT: out BIT);
end thirtytwo_bit_adder;

architecture STRUCTURAL of thirtytwo_bit_adder is

component Full_adder
  port (X, Y: in Bit;
        CIN : in Bit;
        SUM : out Bit;
        COUT : out Bit);
end component;

signal S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15: BIT;
signal S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29: BIT;
signal S30, S31: BIT; 

for all: Full_adder use entity Work.Full_adder(structural);

begin

	U0: Full_adder port map( X => EX(0), Y => EY(0), CIN => ECIN,
				 SUM => ESUM(0), COUT => S1);
	U1: Full_adder port map( X => EX(1), Y => EY(1), CIN => S1,
				 SUM => ESUM(1), COUT => S2);
	U2: Full_adder port map( X => EX(2), Y => EY(2), CIN => S2, 
				 SUM => ESUM(2), COUT => S3);
	U3: Full_adder port map( X => EX(3), Y => EY(3), CIN => S3, 
				 SUM => ESUM(3), COUT => S4);
	U4: Full_adder port map( X => EX(4), Y => EY(4), CIN => S4, 
				 SUM => ESUM(4), COUT => S5);
	U5: Full_adder port map( X => EX(5), Y => EY(5), CIN => S5, 
				 SUM => ESUM(5), COUT => S6);
	U6: Full_adder port map( X => EX(6), Y => EY(6), CIN => S6, 
				 SUM => ESUM(6), COUT => S7);
	U7: Full_adder port map( X => EX(7), Y => EY(7), CIN => S7, 
				 SUM => ESUM(7), COUT => S8);
	U8: Full_adder port map( X => EX(8), Y => EY(8), CIN => S8, 
				SUM => ESUM(8), COUT => S9);
  	U9: Full_adder port map( X => EX(9), Y => EY(9), CIN => S9, 
  				 SUM => ESUM(9), COUT => S10);
  	U10: Full_adder port map( X => EX(10), Y => EY(10), CIN => S10, 
  				 SUM => ESUM(10), COUT => S11);
  	U11: Full_adder port map( X => EX(11), Y => EY(11), CIN => S11, 
  				 SUM => ESUM(11), COUT => S12);
  	U12: Full_adder port map( X => EX(12), Y => EY(12), CIN => S12, 
  				 SUM => ESUM(12), COUT => S13);
  	U13: Full_adder port map( X => EX(13), Y => EY(13), CIN => S13, 
  				 SUM => ESUM(13), COUT => S14);
  	U14: Full_adder port map( X => EX(14), Y => EY(14), CIN => S14, 
  				 SUM => ESUM(14), COUT => S15);
  	U15: Full_adder port map( X => EX(15), Y => EY(15), CIN => S15, 
  				 SUM => ESUM(15), COUT => S16);
  	U16: Full_adder port map( X => EX(16), Y => EY(16), CIN => S16, 
  				 SUM => ESUM(16), COUT => S17);
  	U17: Full_adder port map( X => EX(17), Y => EY(17), CIN => S17, 
  				 SUM => ESUM(17), COUT => S18);
  	U18: Full_adder port map( X => EX(18), Y => EY(18), CIN => S18, 
  				 SUM => ESUM(18), COUT => S19);
  	U19: Full_adder port map( X => EX(19), Y => EY(19), CIN => S19, 
  				 SUM => ESUM(19), COUT => S20);
  	U20: Full_adder port map( X => EX(20), Y => EY(20), CIN => S20, 
  				 SUM => ESUM(20), COUT => S21);
  	U21: Full_adder port map( X => EX(21), Y => EY(21), CIN => S21, 
  				 SUM => ESUM(21), COUT => S22);
  	U22: Full_adder port map( X => EX(22), Y => EY(22), CIN => S22, 
  				 SUM => ESUM(22), COUT => S23);
  	U23: Full_adder port map( X => EX(23), Y => EY(23), CIN => S23, 
  				SUM => ESUM(23), COUT => S24);
  	U24: Full_adder port map( X => EX(24), Y => EY(24), CIN => S24, 
  				 SUM => ESUM(24), COUT => S25);
  	U25: Full_adder port map( X => EX(25), Y => EY(25), CIN => S25, 
  				 SUM => ESUM(25), COUT => S26);
  	U26: Full_adder port map( X => EX(26), Y => EY(26), CIN => S26, 
  				 SUM => ESUM(26), COUT => S27);
  	U27: Full_adder port map( X => EX(27), Y => EY(27), CIN => S27, 
  				 SUM => ESUM(27), COUT => S28);
  	U28: Full_adder port map( X => EX(28), Y => EY(28), CIN => S28, 
  				 SUM => ESUM(28), COUT => S29);
  	U29: Full_adder port map( X => EX(29), Y => EY(29), CIN => S29, 
  				 SUM => ESUM(29), COUT => S30);
  	U30: Full_adder port map( X => EX(30), Y => EY(30), CIN => S30, 
  				 SUM => ESUM(30), COUT => S31);
  	U31: Full_adder port map( X => EX(31), Y => EY(31), CIN => S31, 
  				 SUM => ESUM(31), COUT => ECOUT);

end STRUCTURAL;

 
entity adder32 is
end adder32;

architecture arch of adder32 is

signal A, B, D : Bit_vector(31 downto 0);
signal C, E : Bit;

component Read_in
  port (RX, RY : out Bit_vector(31 downto 0);
        RCIN : out Bit);
end component;

component write_out
  port (RX, RY : in Bit_vector(31 downto 0);
        RCIN : in Bit;
        RSUM : in Bit_vector(31 downto 0);
        RCOUT : in Bit);
end component;

component thirtytwo_bit_adder
  port (EX, EY: in Bit_vector(31 downto 0);
        ECIN : in Bit;
        ESUM : out Bit_vector(31 downto 0);
        ECOUT : out Bit);
end component;

for L1: Read_in use entity Work.Read_in(Read_in_arch);
for L3: write_out use entity Work.write_out(write_out_arch);
for L2: thirtytwo_bit_adder use entity Work.thirtytwo_bit_adder(structural);

begin

L1: Read_in port map(A, B, C);
L3: write_out port map(A, B, C, D, E);
L2: thirtytwo_bit_adder port map(A, B, C, D, E);

end arch;


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