VITAL PROTOTYPE KICKOFF MEETING The VITAL Prototype Kickoff Meeting was held August 2nd at Cadence Design Systems, San Jose CA. The meeting objectives were: a) address how to write accurate, efficient, and compliant ASIC libraries using VITAL defined procedures; b) determine needs for more specific modeling style guidlines; c) develop plans for prototyping & validation phase; and d) strenghen ASIC vendor relationships. Steve Schulz and Victor Berman lead the discussions. There were 42 in attendance, representing the following companies: - ASIC Foundries: Toshiba/Vertex, LSI Logic, NEC, HP, Hitachi, Mitsubishi, SGS-Thomson, National Semi, Siemans, SMOS, and Texas Instruments - EDA Vendors: Cadence, Viewlogic, Synopsys, Ryan & Ryan, Racal-Redac, Vantage, Intergraph, Zycad, Mentor, Ikos, and LMC. Attendees Victor Berman Cadence Graham Davies Viewlogic Bob Foglesong Cadence John Busco Toshiba/Vertex Jefferry Vo LSI Logic Shir-Shen Chang Synopsys Robert Landy NEC Jeff Handong NEC Oz Levia Synopsys Moises Hernandez NEC Ray Ryan Ryan & Ryan Yvonne Ryan Ryan & Ryan Craig Eckel Racal-Redac David Bernstein Vantage Mark Ferris Intergarph Tim Ayres Zycad Russell Iimuka H-P Victor Martin H-P John Sakamoto Hitachi America Yan Xu Mitsubishi Michael A. Bohm Mentor Graphics Ronen Arad Intergraph Marce Carilli SGS-Thomson Allen Chen Mitsubishi Eric Leavitt Cadence Loren Lacy TI Ben Farhat Cadence Stewart Hamilton NEC Anling Hsu Cadence Eugene Ko National Semi Lisa Pia Siemens Gary S. Mattingly Siemens Irene Chang Mitsubishi Baruch Deutsch Intergraph Dave Patel SMOS Mark Clem IKOS Larry Melling IKOS Susan Hardenbrook Zycad Randolph Harr LMC Gene Wu Cadence David Coelho Viewlogic Following a VITAL status update, the need for more strict rules of modeling guidlines was discussed, with a suggestion for 2 levels of VITAL compliance. Many felt the need for numerous example models or a sample cell library, complete with SDF mappings and a sample design. It was suggested that the spec recommend a single way to use the "toolkit" of VITAL features. After much discussion, the group decided that "Level 0" compliance will define a specific minimum set of included (and excluded) features, with the goal of insuring that models will produce the same results in any VHDL-1076 simulator and work with the defined VITAL constructs and external formats. "level 0" compliance summary - VHDL-87 compliant - No simulator specific controls in models - All back annotable objects are VITAL generics - Back annotation will be direct with no computation "Level 1" will further specify additional constraints on modeling style to insure support for acceleration (whether hardware or software) and provide greater consistency (i.e. error messages, delay specification techniques). These levels do NOT specify accuracy (certified, sign-off), which will only be decided by each foundry. "level 1" compliance summary - Includes all "level 0" requirements - Models strictly follow "level 1" modeling guide to be developed in the prototyping activity. It was also re-emphasized that technology parameters, such as needed for slope-dependent delays, are not used in VITAL. All technology data is stored in the foundry's own repository. There was a question over the use of VITAL-defined generics in expressions, such as in the following example: entity e is port (p: out: bit) generic (g: time); end; architecture a of e is constant c: time: 2*g; begin p <= '0' after c; end; After much discussion, the decision was to disallow the use of expessions for timing calculations based on VITAL generics, and issue a warning if detected. This decision was made on the basis that, aside from performance concerns, there could be inconsistencies between an SDF-loaded VITAL simulation and one that loaded it's delays from a VHDL configuration. There were many SDF issues presented and discussed, including: - Cadence SDF (deployed) vs. OVI SDF (planned) - "Subset" VITAL construct support * - Delay values only vs. logic control structures (conditionals)* - OVI change control - Batch file calculation vs. interactive timing modules - Value of preserving SDF as a standard * - OVI's transition to IEEE: when? under what terms? - OVI realizing it's decision impact on other external groups - SDF mapping with CFI's TDDC and EIAJ efforts The most significant issues (asterisks above) centered on the "subset" mapping for VITAL. Three basic levels were identified as options for VITAL: a) map all of SDF ("don't fragment the standard") b) map all but conditionals ("conditionals belong in VHDL") c) just map what's useful/desired for VITAL No consensus could be reached. There seem to be significant differences of opinions over what SDF is, how it is/should be used, and how difficult it is to map into VHDL. As a result, an "SDF sub-team" was established to study the facts, and then present it's findings to educate the group for a later decision. The group did decide on using the OVI v2.0 SDF, in spite of issues over mapping, SDF control not passed to IEEE, and SDF's uncertain future with OVI. Randy Harr provided an update on the VHDL BBS service (vhdl.org). VITAL plans to use this for future distribution of documents and packages (vital@vhdl.org). Much of the afternoon was spent on planning for the prototyping phase of VITAL. The following issues were listed: - Define specific tasks and measures of "success" - Estimate task durations and resource req'ts - Plan for participants and their roles - Form Prototyping sub-team, consisting of: - ASIC suppliers (library development) - EDA simulator vendors (tool development) - End-users (ASIC design development and execution) The team objectives decided were: "Demonstrate a viable, Level-1 compliant design process flow that validates the VITAL specification wth respect to accuracy, efficiency, portability and interoperability." The metrics for success measurement were determined to be: 1) ASIC foundries can map their libraries and technologies to VITAL easily and accurately 2) EDA vendors can accurately and efficiently simulate the VITAL libraries with SDF data 3) End-users can successfully incorporate VITAL libraries in their design process flow for: a) single ASIC library, single simulator b) single ASIC library, multiple simulators c) multiple ASIC libraries, multiple simulators The tasks identified to date are: 1) choose a representative sampling of different macrocell types (using different primitive types); 2) choose sample designs for prototyping with above libraries: - delays are critical - some of the chosen designs must be sharable - small design: easy to understand and publish - large design: proof of performance 3) select participants 4) develop schedules It was decided that detailed plans and schedules should be worked off-line by each sub-team. The following sub-teams were formed: - "Level 1" sub-team (Victor Berman, chair) - SDF sub-team (Bob Foglesong, chair) - Prototyping sub-team (Steve Schulz, chair) Although some teams identified volunteers, final team membership will be determined following a public notice on the VITAL reflector. LSI Logic, Hewlett Packard, and Texas Instruments all offered to participate in generation of VITAL macrocells for a library. Issues to be decided in the prototyping team include synthesizable considerations (for a large sample design), one single, complete library, generation of the SDF files, and mapping with sample design(s). Mentor Graphics offered to provide several circuits, with testbenches, that can be mapped into different target libraries. Action items resulting: - put sub-team recruiting info onto reflector 8/6 - each team leader to writeup objectives/outline 8/13 - each team completes a preliminary schedule 8/27 Many thanks to all who attended, and to Cadence for hosting the event. Regards, Steve Schulz N. American Coordinator, VITAL --------------------------------------------------------------------------- Steven E. Schulz | Member, Group Technical Staff | Internet: ses@asd470.dseg.ti.com Defense Systems Electronics Group | Voice: (214) 575-2720 Texas Instruments | FAX: (214) 575-6807 6500 Chase Oaks Blvd. MS 8420 | Plano, Tx. 75023 | ---------------------------------------------------------------------------