--
-- Rcsid[] = "$Id: vectrgen.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This module is used to put the interrupt vectors on to the 
--  16 bit bus during the INA cycle and RST instruction

entity vectrgen is
port(B16O: out bit_vector(0 to 7);
     INA, RSTN, M3, T2, ACK1, ACK0, I5, I4, I3, GND,VCC: in bit);
end;

architecture structure of vectrgen is

component ocnand
port(O: out bit_vector(0 to 7);
	 I: in bit_vector(0 to 7);
	 ENABLE: in bit);
end component;

component mux_4bit
port(Y: out bit_vector(0 to 3);
	 A,B: in bit_vector(0 to 3);
	 choose: in bit);
end component;

signal mux0, mux1, mux2, mux3: bit;
signal n3, n4, n5, n6, n7: bit;

begin

--U0 : OCNAND port map(B16O(0 to 7), GND,GND,mux3,mux2,mux1,mux0,GND,GND,n4);
U0 : OCNAND port map(B16O(0 to 7), GND,GND,mux0,mux1,mux2,mux3,GND,GND,n4);
U2 : mux_4bit port map(mux0,mux1,mux2,mux3,GND,I3,I4,I5,VCC,ACK0,n3,VCC,INA);
U3 : XOR_gate generic map (1,1) port map(n3,ACK0,ACK1);
U4 : and_gate generic map (1,1) port map(n4,n6,n5);
U5 : nor_gate generic map (1,1) port map(n5,M3,T2);
-- write into PC at end of T2, as 16 bit bus is busy in T3
U6 : or_gate  generic map (1,1) port map(n6,INA,n7);
U7 : inv_gate generic map (1,1) port map(n7,RSTN);

end structure;

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