--
-- Rcsid[] = "$Id: tempctrl.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity tempctrl is
port(HLOUT,WR2TEMP : out bit;
     ID1,ID3,ID4,ID5,ID6,ID7,ID12,ID14,
     ID16,ID17,ID18,ID19,I3,M1,M2,M3,T2,T3,T4: in bit);
end;

architecture structure of tempctrl is

signal n0, n1, n2, ADD_SUB, INR_DCR, n5, DAA, n8, n9: bit;
signal n11, n12, n13, n15, DAD, n17, MVIM : bit;
signal n20, n21, n22, n23, n24, n25, n26: bit;
signal n29,n30, XTHL: bit;

begin
U0 : inv_gate generic map (1,1) port map (n0,ID14);
U1 : inv_gate generic map (1,1) port map (n1,ID6);
U2 : or_gate generic map (1,1) port map (n2,ID17,n1);   -- MOV (r1,r2)
U3 : or_gate generic map (1,1) port map (ADD_SUB,ID18,n1);   -- (reg only)
U4 : or_gate generic map (1,1) port map (INR_DCR,ID16,n0,n5);
U5 : and_gate generic map (1,1) port map (n5,ID4,ID5);
U7 : or_gate generic map (1,1) port map (DAA,ID16,ID12,ID7); -- DAA
U8 : and_gate generic map (1,1) port map (n8,n2,ADD_SUB,INR_DCR,DAA);
U9 : nor_gate generic map (1,1) port map (n9,n8,M1,T4);
U11 : or_gate generic map (1,1) port map (n11,ID19,ID6); -- ADI/SBI/ANI/ORI,data
U12 : or_gate generic map (1,1) port map (n12,ID18,ID6); -- ADD/SUB,ADC/SBB,M,only
U13 : or_gate generic map (1,1) port map (n13,ID16,ID14,n5);
U15 : inv_gate generic map (1,1) port map (n15,I3);
U16 : nor_gate generic map (1,1) port map (DAD,n15,n17,ID16,ID1,T2); -- DAD
U17 : and_gate generic map (1,1) port map (n17,M2,M3);
U18 : or_gate generic map (1,1) port map (MVIM,ID16,ID14,ID6);   -- MVI M,data
U19 : or_gate generic map (1,1) port map (XTHL,ID19,ID12,ID3);  -- XTHL
U20 : and_gate generic map (1,1) port map (n20,n13,MVIM);
U21 : nor_gate generic map (1,1) port map (n21,M2,T3,n20);
U22 : and_gate generic map (1,1) port map (n22,n12,n13);
U23 : and_gate generic map (1,1) port map (n23,n29,n22);
U24 : nor_gate generic map (1,1) port map (n24,M1,T4,n23);
U25 : nor_gate generic map (1,1) port map (n25,n26,M2,T3);
U26 : and_gate generic map (1,1) port map (n26,n22,n11,XTHL,MVIM);
U27 : or_gate generic map (1,1) port map (HLOUT,n24,n21);
U28 : or_gate generic map (1,1) port map (WR2TEMP,n25,n9,DAD);
U29 : or_gate generic map (1,1) port map (n29,ID17,n30);
U30 : xnor_gate generic map (1,1) port map (n30,ID14,ID6);
end structure;

<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br />&nbsp;</div>