-- -- Rcsid[] = "$Id: pc_cntrl.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $"; -- --------------------------------------------- -- pc_cntrl.vhd -- June 19, 1993 --------------------------------------------- entity pc_cntrl is port(WRPC,LOADLATCH,INCRLATCH,PCOUT,LOADMAR,CALL,PCHOUT,PCLOUT, WRPCL,WRPCH,LOADZ,LOADW,ENWZOUT,WRWZINLATCH: out bit; ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11, ID13,ID16,ID19,I3,I5,M1,M2,M3,M4,M5,T2,T3,T4,T6,CC6,LASTMC, RETURNBAR,CCBAR,INA,T1,LHLD: in bit); end; architecture structure of pc_cntrl is signal n0, n1, n2, n3, n4, n5, LXI: bit; signal n11, n12, n15, n18: bit; signal n23, n24, n25, n26, n27, n29: bit; signal n30, n31, n36, n37, RST, n39: bit; signal n40, n46, n47, n49, n56, n59: bit; signal JUMP, JUMPCOND, JUMPCOND_CC: bit; signal CALLWRWZINLAT, JUMPWRWZINLAT: bit; signal JMPCALL, WRPCVEC : bit; signal CALL_buf, CALLCOND, LOADMAR_buf, LOADLATCH_buf: bit; signal WRWZINLATCH_buf, INCRLATCH_buf, LOADW_buf: bit; signal n20b,n20c,n20d: bit; signal M2T3: bit; signal n9, n21a,n21d: bit; signal RET,RET_COND: bit; signal JMPCALL1: bit; begin U0 : or_gate generic map(1,1) port map(n0,ID16,ID6); U1 : or_gate generic map(1,1) port map(n1,ID19,ID6); U2 : or_gate generic map(1,1) port map(n2,ID16,ID2,n3); U3 : inv_gate generic map(1,1) port map(n3,I5); U4 : or_gate generic map(1,1) port map(n4,ID19,ID3,n5); U5 : and_gate generic map(1,1) port map(n5,ID11,ID10); U6 : or_gate generic map(1,1) port map(LXI,ID16,I3,ID1); U7 : or_gate generic map(1,1) port map(JUMP,ID19,ID8,ID3); U8 : or_gate generic map(1,1) port map(CALL_buf,ID19,ID9,ID5); U8a : buf_gate port map (CALL,CALL_buf); U9 : or_gate generic map(1,1) port map(JUMPCOND,ID19,ID2); U9b : or_gate generic map(1,1) port map(JUMPCOND_CC,JUMPCOND,CCBAR); U9a : or_gate port map(n9,ID19,ID4); -- Conditional Call: True or False U10 : or_gate generic map(1,1) port map(CALLCOND,n9,CCBAR); U11 : and_gate generic map(1,1) port map(n11,n0,n1,n4,n12); U12 : and_gate generic map(1,1) port map(n12,n2,LXI,JUMP,JUMPCOND,CALL_buf,n9); U15 : nor_gate generic map(1,1) port map(n15,n12,M2T3); U16 : nor_gate generic map(1,1) port map(LOADLATCH_buf,ID19,ID13,ID1,M1,T1); -- PCHL U16a : buf_gate port map (LOADLATCH,LOADLATCH_buf); U18 : nor_gate generic map(1,1) port map(n18,n11,M1,n25); U19 : or_gate generic map(1,1) port map(WRPC,LOADLATCH_buf,INCRLATCH_buf,WRPCVEC); U20 : NOR_gate generic map(1,1) port map(INCRLATCH_buf,T2,n20b); U20b : AND_gate generic map(1,1) port map(n20b,M1,n20c,n20d); U20c : OR_gate port map(n20c,M2,n11); U20d : OR_gate port map(n20d,M3,n12); U20a : buf_gate port map (INCRLATCH,INCRLATCH_buf); U21 : or_gate generic map(1,1) port map(PCOUT,n18,n15,n59,n49,n21a); -- reload 16bit counter on 1st clock of next inst. --u21a : NOR_gate generic map (1,1) port map(n21a,M1,T1,ID19,ID9,ID1); u21a : NOR_gate generic map (1,1) port map(n21a,M1,T1,n21d); u21b : OR_gate generic map(1,1) port map(RET,ID19,ID9,ID1); -- Return u21c : OR_gate generic map(1,1) port map(RET_COND,ID19,ID0,CCBAR); -- Return Conditional u21d : AND_gate generic map(1,1) port map(n21d,RET,RET_COND); U23 : inv_gate generic map(1,1) port map(n23,CC6); U24 : or_gate generic map(1,1) port map(n24,n23,T6); U25 : and_gate generic map(1,1) port map(n25,n24,n26); U26 : or_gate generic map(1,1) port map(n26,CC6,T4); U27 : or_gate generic map(1,1) port map(n27,M1,n25,LASTMC); U28 : nand_gate generic map(1,1) port map(LOADMAR_buf,n27,n29); U28a : buf_gate port map (LOADMAR,LOADMAR_buf); U29 : or_gate generic map(1,1) port map(n29,T3,LASTMC,n30); U30 : inv_gate generic map(1,1) port map(n30,M1); -- FOR ENABLING THE PCH AND PCL ON TO THE 8 BIT BUS U31 : INV_gate generic map(1,1) port map(n31,RST); U36 : or_gate generic map(1,1) port map(n36,n56,M4,T2); -- PUT PCH ON 8 BIT BUS U37 : or_gate generic map(1,1) port map(n37,n56,M5,T2); -- PUT PCL ON 8 BIT BUS U38 : or_gate generic map(1,1) port map(RST,ID19,ID7); -- FOR RSTn U39 : or_gate generic map(1,1) port map(n39,RST,M2,T2); -- PUT PCH ON 8 BIT BUS U40 : or_gate generic map(1,1) port map(n40,RST,M3,T2); -- PUT PCL ON 8 BIT BUS U41 : nand_gate generic map(1,1) port map(PCHOUT,n39,n36); U42 : nand_gate generic map(1,1) port map(PCLOUT,n40,n37); U43 : nor_gate generic map(1,1) port map(WRPCL,RETURNBAR,M2T3); -- WRITE IN PCL U45 : nor_gate generic map(1,1) port map(WRPCH,RETURNBAR,M3,T3); -- WRITE IN PCH U46 : nor_gate generic map(1,1) port map(n46,M3,T2); -- TO WRITE VECTOR IN RSTn INSTRUCTION U47 : or_gate generic map(1,1) port map(n47,n31,INA); U48 : and_gate generic map(1,1) port map(WRPCVEC,n47,n46); -- WRITE IN M3,T2 -- To load latch for LHLD instr. in M5.T2 with PC contents U49 : nor_gate generic map(1,1) port map(n49,LHLD,M5,T2); U51 : and_gate generic map(1,1) port map(JMPCALL,JUMP,CALL_buf,CALLCOND); U51a : and_gate generic map(1,1) port map(JMPCALL1,JMPCALL,JUMPCOND_CC); U52 : nor_gate generic map(1,1) port map(LOADZ,JMPCALL1,M2T3); U53 : nor_gate generic map(1,1) port map(LOADW_buf,JMPCALL1,M3,T3); U54 : buf_gate port map(LOADW,LOADW_buf); U56 : and_gate generic map(1,1) port map(n56,CALL_buf,CALLCOND); U57 : or_gate generic map(1,1) port map(WRWZINLATCH_buf,CALLWRWZINLAT,JUMPWRWZINLAT); U57a : buf_gate port map (WRWZINLATCH,WRWZINLATCH_buf); U58 : or_gate generic map(1,1) port map(ENWZOUT,LOADW_buf,WRWZINLATCH_buf); U59 : and_gate generic map(1,1) port map(n59,JMPCALL1,LOADMAR_buf); U60 : nor_gate generic map(1,1) port map(CALLWRWZINLAT,n56,M5,T3); U61 : nor_gate generic map(1,1) port map(JUMPWRWZINLAT,JMPCALL1,M1,T1); U62 : OR_gate port map(M2T3,M2,T3); end structure;