--
-- Rcsid[] = "$Id: intrupt3.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

---------------------------------------------
-- intrupt3.vhd
-- June 18, 1993
---------------------------------------------

-- This logic is responsible for the serial input and output
-- functions and also for storing the INTE flip flop's value
-- before an occurance of TRAP.

entity intrupt3 is
port(BUSOUT: out bit_vector(0 to 7);
     SOD,SIM: out bit;
     ACK: in bit_vector(2 downto 0);
     CK,CKBAR,M1,T3,T2,ID16,ID14,ID12,ID0,MASK75SET,MASK65SET,
     MASK55SET,RST55,RST65,RST75SET,SID,RESET,EI,BUSIN6,BUSIN7,VCC: in bit);
end;

architecture structure of intrupt3 is

component ocnand
port(O: out bit_vector(7 downto 0);
	 I: in bit_vector(7 downto 0);
	 ENABLE: in bit);
end component;

signal n1, n2, n3, n4a, n4b, n5, n6, n7, n8, n9: bit;
signal n11, RIM, n14, n15: bit;
signal L1, L2, L3, L4: bit;
signal SIMB: bit;

begin
U1 : nor_gate generic map(1,1) port map(n1,ACK(2),ACK(1),ACK(0));
U2 : or_gate generic map(1,1) port map(n2,T3,CK,M1,RIM);
U3 : and_gate generic map(1,1) port map(n3,RESET,n2);
U4 : DFF1 port map(L1,n1,CKBAR,VCC,n3);
U4a : inv_gate port map(L2, L1);
U5 : and_gate generic map(1,1) port map(n5,n4b,CK);
U6 : DFF1 port map(L3,EI,n5,VCC,n3);
U7 : and_gate generic map(1,1) port map(n7,n4a,n6);
U8 : or_gate generic map(1,1) port map(n8,n7,n9);
U9 : and_gate generic map(1,1) port map(n9,EI,n4b);
U10 : nor_gate generic map(1,1) port map(SIMB,ID0,ID14,ID16);
U10a : buf_gate port map(SIM,SIMB);
U11 : and_gate generic map(1,1) port map(n11,SIMB,BUSIN6,BUSIN7,n14);
U12 : DFF1 port map(L4,n11,CKBAR,VCC,RESET);
U13 : or_gate generic map(1,1) port map(RIM,ID0,ID12,ID16);
U14 : inv_gate generic map(1,1) port map(n14,T2);
U15 : nor_gate generic map(1,1) port map(n15,RIM,T2);
U16 : OCNAND port map(BUSOUT(0 to 7),
			 MASK55SET,MASK65SET,MASK75SET,n8,RST55,RST65,RST75SET,SID,n15);
U30 : buf_gate generic map (2,2) port map(n4a,L1);
U31 : buf_gate generic map (2,2) port map(n4b,L2);
U32 : buf_gate generic map (2,2) port map(n6,L3);
U33 : buf_gate generic map (2,2) port map(SOD,L4);
end structure;

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