-- -- Rcsid[] = "$Id: flagunit.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $"; -- -- flagunit.vhd -- June 3, 1993 -- -- This module contains the flag registers and flag control logic. -- entity flagunit is port(BUSOUT0,BUSOUT4,BUSOUT6,BUSOUT2,BUSOUT7, MUXCC,MUXCCBAR,ALUCYOUT,AC_SET: out bit; M3,M2,M1,T4,T3,T2, IBUS0,IBUS2,IBUS4,IBUS6,IBUS7,ALUCRYIN,ACFLAG,ZFLAG, PFLAG,SFLAG,I3,CLKBAR,GND,VCC, ID1,ID4,ID5,ID6,ID7,ID8,ID9,ID10, ID11,ID12,ID13,ID14,ID15,ID16,ID18,ID19: in bit); end; architecture structure of flagunit is component mux_4bit port(Y: out bit_vector(0 to 3); A,B: in bit_vector(0 to 3); choose: in bit); end component; signal E0, E1, F4: bit; signal n1, PUSH_PSW, n3, n4, n5, n7, n8, M2T2, n132: bit; signal QMUX,FLAG_BUS: bit_vector(0 to 3); signal CARRY, AUX_CARRY, ZERO_DETECT, PARITY, SIGN, G1, G3, G4, G5: bit; signal MUXCC_buf: bit; signal p2, p3, p5, p6: bit; signal p10, POP_PSW, p12, p13, p14, DAD, p16: bit; signal p19, p20, p21, p22, p23, p24, p25, p26: bit; signal p29, DAA, p31, p32, p33, p41: bit; signal F3, ALU_OPS_: bit; signal n48, n49, n50, n51, n52, n53, n54, n55: bit; begin U1 : inv_gate generic map(2,2) port map(n1,F4); U2 : nor_gate generic map(2,2) port map(PUSH_PSW,ID19,ID14,ID5); -- PUSH PSW U3 : and_gate generic map(2,2) port map(n3,IBUS0,F4); U4 : and_gate generic map(2,2) port map(n4,n1,ALUCRYIN); U5 : or_gate generic map(2,2) port map(n5, n3,n4); U6 : mux_4bit port map(QMUX(0 to 3),ACFLAG,ZFLAG,PFLAG,SFLAG,IBUS4,IBUS6,IBUS2,IBUS7,F4); U7 : and_gate generic map(2,2) port map(n7,M2T2,PUSH_PSW); U8 : and_gate generic map(2,2) port map(n8,E1,CLKBAR); -- Hold current value if E0 is 0. U10 : mux_4bit port map(FLAG_BUS(0 to 3),AUX_CARRY,ZERO_DETECT, PARITY,SIGN,QMUX(0 to 3),E0); U13 : DFF1 port map(CARRY,n5,n8,n132,VCC); U131 : inv_gate port map(G1,CARRY); U132 : or_gate generic map (1,1) port map(n132,ID7,ID14,ID16,T2); U14 : DFF1 port map(AUX_CARRY,FLAG_BUS(0),CLKBAR,VCC,VCC); U15 : DFF1 port map(ZERO_DETECT,FLAG_BUS(1),CLKBAR,VCC,VCC); U15a : inv_gate port map(G3,ZERO_DETECT); U16 : DFF1 port map(PARITY,FLAG_BUS(2),CLKBAR,VCC,VCC); U16a : inv_gate port map(G4,PARITY); U17 : DFF1 port map(SIGN,FLAG_BUS(3),CLKBAR,VCC,VCC); U17a : inv_gate port map(G5,SIGN); U18 : nand_gate generic map (2,2) port map(BUSOUT0,CARRY,n7); -- CY (carry) U19 : nand_gate generic map (2,2) port map(BUSOUT4,AUX_CARRY,n7); -- AC (aux. carry) U20 : nand_gate generic map (2,2) port map(BUSOUT6,ZERO_DETECT,n7); -- Z (zero detect) U21 : nand_gate generic map (2,2) port map(BUSOUT2,PARITY,n7); -- P (parity) U22 : nand_gate generic map (2,2) port map(BUSOUT7,SIGN,n7); -- S (sign) U24 : nor_gate generic map (2,2) port map(M2T2,M2,T2); U27a : buf_gate port map (ALUCYOUT,CARRY); U28a : buf_gate port map (AC_SET,AUX_CARRY); -- -- Select the condition code, based on the value of op-code bits I5,I4,I3 -- U47 : AND_gate generic map(1,1) port map(MUXCC_buf,n48,n49,n50,n51,n52,n53,n54,n55); U48 : OR_gate generic map(1,1) port map(n48,CARRY,ID11); -- C_bar U49 : OR_gate generic map(1,1) port map(n49,G1, ID10); -- C U50 : OR_gate generic map(1,1) port map(n50,ZERO_DETECT,ID9); -- Z_bar U51 : OR_gate generic map(1,1) port map(n51,G3, ID8); -- Z U52 : OR_gate generic map(1,1) port map(n52,PARITY,ID13); -- P_bar U53 : OR_gate generic map(1,1) port map(n53,G4,ID12); -- P U54 : OR_gate generic map(1,1) port map(n54,SIGN,ID15); -- S_bar U55 : OR_gate generic map(1,1) port map(n55,G5,ID14); -- S U60 : inv_gate generic map(1,1) port map(MUXCCBAR,MUXCC_buf); U61 : buf_gate port map(MUXCC,MUXCC_buf); V2 : inv_gate generic map(2,2) port map(p2,ID14); V3 : and_gate generic map(2,2) port map(p3,ID4,ID5); V4 : nor_gate generic map(2,2) port map(F3,M1,T2); V5 : and_gate generic map(2,2) port map(p5,ID8,ID9,ID10,ID11,ID15); V6 : and_gate generic map(2,2) port map(p6,M2,M3); V10 : nor_gate generic map(2,2) port map(p10,M2,T3); V11 : nor_gate generic map(2,2) port map(POP_PSW,ID19,ID1,ID14); -- POP PSW V12 : nor_gate generic map(2,2) port map(p12,ID16,p3,p2); -- INR/DCR r V13 : nor_gate generic map(2,2) port map(p13,ID16,p3,ID14); -- INR/DCR M V14 : nor_gate generic map(2,2) port map(p14,ID16,ID7,p5); -- RAL/RAR/RLC/RRC CMC/STC V15 : nor_gate generic map(2,2) port map(DAD,ID16,ID1,p33); -- DAD V16 : nor_gate generic map(2,2) port map(p16,T3,p6); V18 : and_gate generic map(2,2) port map(F4,p10,POP_PSW); V19 : and_gate generic map(2,2) port map(p19,F3,p12); V20 : and_gate generic map(2,2) port map(p20,p10,p13); V21 : and_gate generic map(2,2) port map(p21,p14,F3); V22 : and_gate generic map(2,2) port map(p22,DAD,p16); V23 : and_gate generic map(2,2) port map(p23,ALU_OPS_,F3); V24 : or_gate generic map(2,2) port map( p24,p19,p20); V25 : or_gate generic map(2,2) port map( p25,p23,F4,p32); V26 : or_gate generic map(2,2) port map( p26,p21,p22); V27 : or_gate generic map(2,2) port map( E0, p24,p25); V28 : or_gate generic map(2,2) port map( E1, p25,p26); V29 : nor_gate generic map(2,2) port map(p29,M1,T4); V30 : nor_gate generic map(2,2) port map(DAA,ID7,ID12,ID16); -- DAA V31 : or_gate generic map(2,2) port map(p31,p29,F3); V32 : and_gate generic map(2,2) port map(p32,p31,DAA); V33 : inv_gate generic map(1,1) port map(p33,I3); V40 : NAND_gate port map(ALU_OPS_,ID18,p41); V41 : OR_gate port map(p41,ID19,ID6); end structure;