--
-- Rcsid[] = "$Id: ctl_lgc2.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This logic is responsible for generating the T states,
-- the machine cycles and the HALT and HOLD states.

entity ctl_lgc2 is
port(Q: out bit_vector(4 downto 0);
     RESETBAR,W1,W2,W3,W4,W5,W6,RESETOUT,HLDA: out bit;
     CLK,RESETIN,INSTRESET,HOLD,READY,VINT,CC6,BIMC,ID17,
     ID14,ID6,GND,VCC,CLKBAR: in bit;
     THALT, THOLD, TWAIT: out bit);
end;

architecture structure of ctl_lgc2 is

component M5
port(Q: out logic_vector(4 downto 0);
	 CKN,VCC,SYSRESET,INSTRESET: in bit);
end component;

component stater
port(W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,RESETOUT: out bit;
     HLDA,HLTA,READY,VINT,CLK,RESETIN,GND,VCC,CC6,BIMC,M1: in bit);
end component;

component hldlogic
port(HLDA : out bit;
     CLK,HOLD,TRESET,T2,T4,THALT,VCC: in bit);
end component;

component hltlogic
port(HLTA: out bit;
     ID17,ID14,ID6,T4,CLK,TRESET,VINT,VCC: in bit);
end component;

signal im1, HLTA: bit;
signal W1_buf, W2_buf, W4_buf, RESETBAR_buf, HLDA_buf: bit;
signal Q0_buf, THALT_buf: bit;

begin
M0 : M5  port map(Q(4 downto 1),Q0_buf,W1_buf,VCC,RESETBAR_buf,INSTRESET);

U1 : STATER  port map(RESETBAR_buf,W1_buf,W2_buf,W3,W4_buf,W5,W6,TWAIT,
             THALT_buf,THOLD,RESETOUT,HLDA_buf,HLTA,READY,VINT,CLK,
             RESETIN,GND,VCC,CC6,BIMC,im1);
U2 : INV_gate generic map(1,1) port map(im1,Q0_buf);

HDL : HLDLOGIC port map(HLDA_buf,CLKBAR,HOLD,RESETIN,W2_buf,W4_buf,
                        THALT_buf,VCC);
HTL : HLTLOGIC port map(HLTA,ID17,ID14,ID6,W4_buf,CLKBAR,
                        RESETBAR_buf,VINT,VCC);

buf1 : buf_gate port map (W1,W1_buf);
buf2 : buf_gate port map (RESETBAR,RESETBAR_buf);
buf3 : buf_gate port map (HLDA,HLDA_buf);
buf4 : buf_gate port map (Q(0),Q0_buf);
buf5 : buf_gate port map (W2,W2_buf);
buf6 : buf_gate port map (W4,W4_buf);
buf7 : buf_gate port map (THALT,THALT_buf);
end structure;

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