--
-- Rcsid[] = "$Id: ctl_lgc1.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

---------------------------------------------
--  May 22, 1993
--  ctl_lgc1
---------------------------------------------

--   This logic generates the read, write, ALE, INTABAR, IOMBAR, S1,
--   S0  etc.  The components mcdecoder1 and mcdecoder2 are used to
--   generate signals depending on the instruction type for resetting
--   the M5 counter after appropriate machine cycles.


entity ctl_lgc1 is
port(m5reset,lastmc,RSTN,ALE,RDBAR,WRBAR,INTABAR,IOMBAR,S1,S0,BIMC,
	 CC6_signal: out bit;
	 ID: in bit_vector(19 downto 0);
	 CC,CCbar,I2,I3,I5,M5,M4,M3,M2,M1,
     T1,T2,T3,CLKBAR,CLK,VCC,INA,INTA,RESETBAR: in bit);
end;

architecture structure of ctl_lgc1 is

component mcdecode
port(m5reset,wrinm2,wrinm3,lastmc,rstn,CC6: out bit;
	 ID: in bit_vector(19 downto 0);
     CC,CCbar,I2,I3,I5,M1,M2,M3,M4,M5,INA: in bit);
end component;

component rdwrgen
port(ALE,RDBAR,WRBAR,INTABAR,IOMBAR,S1,S0,BIMC: out bit;
     T3,T2,T1,CLKBAR,CLK,wrinm2,wrinm3,ID19,ID16,ID15,ID13,
	 ID11,ID10,ID9,ID5,ID4,ID3,ID2,ID1,I3,
     INA,INTA,CCBAR,RESETBAR,VCC: in bit;
     M: in bit_vector(5 downto 1));
end component;

signal wrinm2, wrinm3: bit;

begin
M_2 : mcdecode port map(m5reset,wrinm2,wrinm3,lastmc,RSTN,CC6_signal,
			            ID(19 downto 0),CC,CCbar,I2,I3,I5,M1,M2,M3,M4,M5,INA);
RW : rdwrgen port map(ALE,RDBAR,WRBAR,INTABAR,IOMBAR,S1,S0,BIMC,T3,T2,T1,CLKBAR,
            CLK,wrinm2,wrinm3,ID(19),ID(16),ID(15),ID(13),ID(11 downto 9),
			ID(5 downto 1),I3,INA,INTA,CCBAR,RESETBAR,VCC,M5,M4,M3,M2,M1);
end structure;

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