TDX/FSIM Simulator ASI Release 3.0 - Sun4 SunOS 4.1.x gl85 Tue Oct 5 16:38:25 1993 Commands executed from file gl85.tdxinit. (echo) hyperactive 0 (echo) hypertrophic 0 (echo) bus ALU_A_IN hex AL/A__7 AL/A__6 AL/A__5 AL/A__4 AL/A__3 AL/A__2 AL/A__1 AL/A__0 (echo) bus ALU_B_IN hex AL/B__7 AL/B__6 AL/B__5 AL/B__4 AL/B__3 AL/B__2 AL/B__1 AL/B__0 (echo) bus ALU_F_OUT hex AL/F__7 AL/F__6 AL/F__5 AL/F__4 AL/F__3 AL/F__2 AL/F__1 AL/F__0 (echo) bus ALU_FUNCTION hex AL/S3 AL/S2 AL/S1 AL/S0 (echo) bus ALUOUT hex AL/SH_L/Y2__3 AL/SH_L/Y2__2 AL/SH_L/Y2__1 AL/SH_L/Y2__0 AL/SH_L/Y3__3 AL/SH_L/Y3__2 AL/SH_L/Y3__1 AL/SH_L/Y3__0 (echo) bus MDR_IN hex DA/D__7 DA/D__6 DA/D__5 DA/D__4 DA/D__3 DA/D__2 DA/D__1 DA/D__0 (echo) bus 16BITCTR hex RPD/G16CTR/U13/QD_BUF RPD/G16CTR/U13/QC_BUF RPD/G16CTR/U13/QB_BUF RPD/G16CTR/U13/QA_BUF RPD/G16CTR/U10/QD_BUF RPD/G16CTR/U10/QC_BUF RPD/G16CTR/U10/QB_BUF RPD/G16CTR/U10/QA_BUF RPD/G16CTR/U7/QD_BUF RPD/G16CTR/U7/QC_BUF RPD/G16CTR/U7/QB_BUF RPD/G16CTR/U7/QA_BUF RPD/G16CTR/U4/QD_BUF RPD/G16CTR/U4/QC_BUF RPD/G16CTR/U4/QB_BUF RPD/G16CTR/U4/QA_BUF (echo) bus PC_REG hex RPD/BCPS/QP__15 RPD/BCPS/QP__14 RPD/BCPS/QP__13 RPD/BCPS/QP__12 RPD/BCPS/QP__11 RPD/BCPS/QP__10 RPD/BCPS/QP__9 RPD/BCPS/QP__8 RPD/BCPS/QP__7 RPD/BCPS/QP__6 RPD/BCPS/QP__5 RPD/BCPS/QP__4 RPD/BCPS/QP__3 RPD/BCPS/QP__2 RPD/BCPS/QP__1 RPD/BCPS/QP__0 (echo) bus DN_BUS hex RPD/DN__15 RPD/DN__14 RPD/DN__13 RPD/DN__12 RPD/DN__11 RPD/DN__10 RPD/DN__9 RPD/DN__8 RPD/DN__7 RPD/DN__6 RPD/DN__5 RPD/DN__4 RPD/DN__3 RPD/DN__2 RPD/DN__1 RPD/DN__0 (echo) bus ACCUMULATOR hex AL/OP_L/AC__7 AL/OP_L/AC__6 AL/OP_L/AC__5 AL/OP_L/AC__4 AL/OP_L/AC__3 AL/OP_L/AC__2 AL/OP_L/AC__1 AL/OP_L/AC__0 (echo) bus TEMP_REG hex AL/OP_L/TEMP_REG/R7 AL/OP_L/TEMP_REG/R6 AL/OP_L/TEMP_REG/R5 AL/OP_L/TEMP_REG/R4 AL/OP_L/TEMP_REG/R3 AL/OP_L/TEMP_REG/R2 AL/OP_L/TEMP_REG/R1 AL/OP_L/TEMP_REG/R0 (echo) bus ACC_TEMP hex AL/OP_L/AUX_ACC/R7 AL/OP_L/AUX_ACC/R6 AL/OP_L/AUX_ACC/R5 AL/OP_L/AUX_ACC/R4 AL/OP_L/AUX_ACC/R3 AL/OP_L/AUX_ACC/R2 AL/OP_L/AUX_ACC/R1 AL/OP_L/AUX_ACC/R0 (echo) bus B_REG hex RPD/BCPS/QB__15 RPD/BCPS/QB__14 RPD/BCPS/QB__13 RPD/BCPS/QB__12 RPD/BCPS/QB__11 RPD/BCPS/QB__10 RPD/BCPS/QB__9 RPD/BCPS/QB__8 (echo) bus C_REG hex RPD/BCPS/QB__7 RPD/BCPS/QB__6 RPD/BCPS/QB__5 RPD/BCPS/QB__4 RPD/BCPS/QB__3 RPD/BCPS/QB__2 RPD/BCPS/QB__1 RPD/BCPS/QB__0 (echo) bus D_REG hex RPD/HLDEW/QD__15 RPD/HLDEW/QD__14 RPD/HLDEW/QD__13 RPD/HLDEW/QD__12 RPD/HLDEW/QD__11 RPD/HLDEW/QD__10 RPD/HLDEW/QD__9 RPD/HLDEW/QD__8 (echo) bus E_REG hex RPD/HLDEW/QD__7 RPD/HLDEW/QD__6 RPD/HLDEW/QD__5 RPD/HLDEW/QD__4 RPD/HLDEW/QD__3 RPD/HLDEW/QD__2 RPD/HLDEW/QD__1 RPD/HLDEW/QD__0 (echo) bus H_REG hex RPD/HLDEW/QH__15 RPD/HLDEW/QH__14 RPD/HLDEW/QH__13 RPD/HLDEW/QH__12 RPD/HLDEW/QH__11 RPD/HLDEW/QH__10 RPD/HLDEW/QH__9 RPD/HLDEW/QH__8 (echo) bus L_REG hex RPD/HLDEW/QH__7 RPD/HLDEW/QH__6 RPD/HLDEW/QH__5 RPD/HLDEW/QH__4 RPD/HLDEW/QH__3 RPD/HLDEW/QH__2 RPD/HLDEW/QH__1 RPD/HLDEW/QH__0 (echo) bus Z_REG hex RPD/HLDEW/WZ_PAIR/U0/R7 RPD/HLDEW/WZ_PAIR/U0/R6 RPD/HLDEW/WZ_PAIR/U0/R5 RPD/HLDEW/WZ_PAIR/U0/R4 RPD/HLDEW/WZ_PAIR/U0/R3 RPD/HLDEW/WZ_PAIR/U0/R2 RPD/HLDEW/WZ_PAIR/U0/R1 RPD/HLDEW/WZ_PAIR/U0/R0 (echo) bus W_REG hex RPD/HLDEW/WZ_PAIR/U1/R7 RPD/HLDEW/WZ_PAIR/U1/R6 RPD/HLDEW/WZ_PAIR/U1/R5 RPD/HLDEW/WZ_PAIR/U1/R4 RPD/HLDEW/WZ_PAIR/U1/R3 RPD/HLDEW/WZ_PAIR/U1/R2 RPD/HLDEW/WZ_PAIR/U1/R1 RPD/HLDEW/WZ_PAIR/U1/R0 (echo) bus SP_REG hex RPD/BCPS/QS__15 RPD/BCPS/QS__14 RPD/BCPS/QS__13 RPD/BCPS/QS__12 RPD/BCPS/QS__11 RPD/BCPS/QS__10 RPD/BCPS/QS__9 RPD/BCPS/QS__8 RPD/BCPS/QS__7 RPD/BCPS/QS__6 RPD/BCPS/QS__5 RPD/BCPS/QS__4 RPD/BCPS/QS__3 RPD/BCPS/QS__2 RPD/BCPS/QS__1 RPD/BCPS/QS__0 (echo) bus DATA_IN hex DIN__7 DIN__6 DIN__5 DIN__4 DIN__3 DIN__2 DIN__1 DIN__0 (echo) bus ADDRESS_BUS hex A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (echo) bus B8BO_bus hex B8BO__7 B8BO__6 B8BO__5 B8BO__4 B8BO__3 B8BO__2 B8BO__1 B8BO__0 (echo) bus B8BIN_bus hex B8BIN__7 B8BIN__6 B8BIN__5 B8BIN__4 B8BIN__3 B8BIN__2 B8BIN__1 B8BIN__0 (echo) bus B16BIN_bus hex B16BIN__15 B16BIN__14 B16BIN__13 B16BIN__12 B16BIN__11 B16BIN__10 B16BIN__9 B16BIN__8 B16BIN__7 B16BIN__6 B16BIN__5 B16BIN__4 B16BIN__3 B16BIN__2 B16BIN__1 B16BIN__0 (echo) bus INST_REG hex IR/B8/R0 IR/B8/R1 IR/B8/R2 IR/B8/R3 IR/B8/R4 IR/B8/R5 IR/B8/R6 IR/B8/R7 (echo) bus M_bus hex M5 M4 M3 M2 M1 (echo) bus T_bus hex T6 T5 T4 T3 T2 T1 (echo) vector print CLK $ DATA_IN $ ADDRESS_BUS $ THALT TWAIT THOLD $ T6 T5 T4 T3 T2 T1 $ M5 M4 M3 M2 M1 $ PC_REG $ B_REG $ C_REG $ D_REG $ E_REG $ H_REG $ L_REG $ SP_REG $ INST_REG $ ACCUMULATOR $ Z_REG $ W_REG $ AL/FG_U/CARRY AL/FG_U/AUX_CARRY AL/FG_U/ZERO_DETECT AL/FG_U/PARITY AL/FG_U/SIGN $ TEMP_REG $ ACC_TEMP $ B8BO_bus $ B16BIN_bus $ BOUT $ B8BIN_bus $ $ DN_BUS $ WRSP WRPC WRPCL WRPCH RGC/PCC/WRPCVEC $ RDBAR WRBAR WR2TEMP $ MDR_IN $ S1 S0 ALE $ SEL_CNTR SEL16BUS $ DECRLATCH INCRLATCH $ WRZ WRW WRWZ $ WZOUT DEOUT HLOUT SPOUT PCOUT BCOUT $ ALUOUTEN AL/FG_U/N7 ACCOUTEN IT/F2/N15 DOUT EOUT HOUT LOUT SP1OUT SP0OUT PCHOUT PCLOUT BOUT COUT MDROUT TEMP_OUT $ ENLATCHOUT RGC/INCRLATCH_BUF RGC/DECRLATCH_BUF RGC/ENLATCHOUT0 $ PCOUT RGC/PCC/N18 RGC/PCC/N15 RGC/PCC/N59 RGC/PCC/N49 RGC/PCC/N21A Simulation stopping at time 9100000 because of no more input vectors. Simulation stopping during vector 2276. Simulation terminating at timestep = 9100000 MODEL PARAMETERS design name = gl85 outfile design name = gl85.fsim in port count = 20 out port count = 27 net count = 3004 dead net count = 18 undriven net count = 0 element count = 2984 equiv element count = 5394 zero delay elements = 422 vl behavior flag = off design file date = Tue Oct 5 16:37:48 1993 (749864268) MEMORY USAGE PARAMETERS bytes from heap = 3512613 bytes for symbols = 120780 bytes for events = 88584 bytes for FOs = 259488 bytes for FEs = 2472072 COMMAND VARIABLES cycle time = 4000 strobe time = 0 max delta = 2000 max oscillations = 0 oscillation limit = 0 ram x address limit = 8 ram x report limit = 1000 initial state value = PX print time spt = off print all changes = vector unstable show events = on unstable cancel = on breakpoint unknowns = off stable conflict = off stable conflict rept = report compare outputs = on vector file name = gl85.vec tvc file name = null wgl file name = null tstl file name = null spt file name = gl85.fsim.spt plot order file name = null source cmd file name = null SCHEDULER PARAMETERS number of vectors = 2275 timestep = 9100000 events scheduled = 364033 events executed = 364023 events cancelled = 10 events altered = 2524 zero delay events = 44417 nonzero delay events = 319616 evaluations = 1144482 macro tq event count = 0 event records = 3691 unstable count = 0 ram x address count = 0 ram addrdata records = 0 ram evaluations = 0 min clock cycle req = 63 timeplate name = DEFAULT_TIMEPLATE FSIM COMMAND VARIABLES fault file name = gl85.flt hard detection limit = 1 probable limit = 5 hyperactive limit = 0 hypertrophic limit = 0 resimulate probables = off resimulate hyper = off keep sim probables = off tester detects Zs = on detect strength = on accelerate mode = 0 unstable cancel flts = on FSIM PARAMETERS faults detectable = 5406 faults detected = 3734 faults probable = 245 faults hyperactive = 0 faults oscillating = 0 faults undetectable = 0 faults suspended = 0 faults ignored = 0 total faults detected = 3979 fault evaluations = 11452180 fault events scheduled = 2475980 fault events executed = 2458205 fault events cancelled = 17775 alloc fault effects = 103003 used fault effects = 6006 visible fault effects = 1237 visible fault origins = 170 fault pool activity = 60012 fault pool sorts = 28 fault pool sort limit = 60 fault ram evaluations = 0 fault ram records = 0 fault ram eval hazards = 0 Invoked with: tdx_fsim gl85 -T -o -om gl85.fsim +-----------------------------------------+ | times in hours:min:sec | | | | setup cpu time = 00:00:00 | | simul cpu time = 00:04:44 | | total cpu time = 00:04:44 | | setup elapsed time = 00:00:02 | | simul elapsed time = 00:04:47 | | total elapsed time = 00:04:49 | | | +-----------------------------------------+ NUMBER OF VECTORS = 2275 NUMBER OF DETECTABLE FAULTS = 5406 NUMBER OF FAULTS DETECTED = 3734 FAULT COVERAGE = 69.071 % NUMBER OF PROBABLE DETECTS = 245 TOTAL FAULTS DETECTED (DETECT + PROBABLE) = 3979 TOTAL FAULT COVERAGE (DETECT + PROBABLE) = 73.603 %