-- -----------------------------------------------------------------------------
--  EPF10K10LC84B - TOP LEVEL ENTITY frame design for our FPGA-Praktikum      --
-- -----------------------------------------------------------------------------
--
--  File        : 'epf10k10lc84b.vhd' (RSA processor)
--  Author      :  Lars Larsson, Lars H. Hahn 
-- 
--  Date        : Feb 4, 1999 (Version 2.1)
--
--  Description : This is a design frame - the top level design for synthesis -
--                for your own designs provided for the in-system programmable 
--                Altera EPF10K10LC84-3 EPLD. The data sheet of this FPGA is 
--                available worldwide under http://www.altera.com/ and locally 
--                (domain informatik.uni.hamburg.de) under http://tech-www/00sheets/
--
--  Hint        : You MUST NOT change anything within this design frame. Use the 
--                ACF file 'epf10k10lc84b.acf' while synthesis with MAX+plusII !
--
-- -----------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
--                                  University of Hamburg
--                                  Vogt-Koelln-Str. 30
--                                  D - 22041 Hamburg, Germany
--                                  larsson@informatik.uni-hamburg.de
--                                  http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
-- -----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

   use work.chips.all;                     -- CHIPs (EPLD and FPGAs) DEFINITIONS 

   entity epf10k10lc84b is                 -- Flex10K FPGA B (RSA processor)
     port(       
                  clk :    in std_ulogic;  -- clock = 16 MHz quartz oscillator
                 nrst :    in std_ulogic;  -- *reset (automatic power-on reset)

        nsend_receive :    in std_ulogic;  -- send/receive selection (0:send,1:receive)
              to_flex :    in std_ulogic;  -- define direction of data (0:read from FLEX, 1:write into FLEX)

              request :    in std_ulogic;  -- request to process (=>send)
                 send :   out std_ulogic;  -- start sending      (=>request)

                 hold :    in std_ulogic;  -- hold (not enable)  (=>busy)
                 busy :   out std_ulogic;  -- busy indicator     (=>hold)

           char_inout : inout std_logic_vector (7 downto 0); -- bidirectional data stream (nsend_receive)

              data_in :    in std_ulogic;
             data_out :   out std_ulogic
         );

   end epf10k10lc84b;

architecture structure of epf10k10lc84b is

   signal char_in_s, char_out_s : std_logic_vector (7 downto 0);

   begin

      --  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
      -- connection of TriState port of the EPF10K10LC84 FPGA to signals within this architecture ---------

      tristate_p: process ( nsend_receive, to_flex, char_out_s )
                  begin
                    if (nsend_receive='0' AND to_flex='0') then -- write to bus (drive data)
                        char_inout <= char_out_s;
                    else                                        -- read data
                        char_inout <= (others=>'Z'); 
                    end if;
                  end process;

      char_in_s <= char_inout;                                  -- read data from Tristate bus 

      flexb_i : flexb port map ( clk => clk, nrst => nrst, nsend_receive => nsend_receive,
                                 request => request, send => send, busy => busy, hold => hold,
                                 char_in => char_in_s, char_out => char_out_s,
                                 data_in => data_in, data_out => data_out );
   end structure;

-- ---------------------------------------------------------------------------------------------------------

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