-- -----------------------------------------------------------------------------
-- BOARD LEVEL SIMULATION - ENTITY for our FPGA-Praktikum --
-- -----------------------------------------------------------------------------
--
-- File : 'board.vhd'
-- Author : Lars Larsson
--
-- Date : February 9, 1999
--
-- Description : This is a VHDL frame of our board for board level simulation.
--
-- -----------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
-- University of Hamburg
-- Vogt-Koelln-Str. 30
-- D - 22041 Hamburg, Germany
-- larsson@informatik.uni-hamburg.de
-- http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.components.all; -- COMPONENT DEFINITIONS
use work.simulation.all; -- SIMULATION COMPONENT DEFINITIONS
use work.chips.all; -- CHIPS DEFINITIONS
entity board is
port(
clk : in std_ulogic; -- clock = 16 MHz
nrst : in std_ulogic; -- *reset
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive)
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1')
dip_switches : in std_ulogic_vector (7 downto 0); -- [DIP-Switches 1-2-3-4-5-6-7-8]
led_array : out std_ulogic_vector (7 downto 0) -- 8 x LED array (high active)
);
end board;
architecture structure of board is
-- SIGNAL DEFINITIONS HERE ---------------------------------------------------------------------------------
signal clk_s, nrst_s : std_ulogic; -- clock and reset signal
signal rs232_txd_s, rs232_rxd_s : std_ulogic; -- RS232 signals
signal irda_rxda_s, irda_txd_s : std_ulogic; -- IrDA signals
signal nsend_receive_s : std_ulogic; -- nsend_receive selection signal
signal baud_rate_select_s : std_ulogic_vector (2 downto 0); -- baud rate selection signals
signal dip_switches_s : std_ulogic_vector ( 7 downto 0); -- 8 x DIP switch (blue)
signal led_array_s : std_ulogic_vector ( 7 downto 0); -- 8 x LED array (yellow)
signal nkey_s : std_ulogic; -- strobe key (red)
signal data_s : std_logic_vector ( 7 downto 0); -- RAM data bus of RAM / LED array
signal address_s : std_ulogic_vector (10 downto 0); -- address bus from EPLD
signal sram_address_s : std_logic_vector (14 downto 0); -- address bus to SRAM
signal nwe_s : std_ulogic; -- write enable signal for SRAM & DRAM
signal noe_s : std_ulogic; -- output enable signal for SRAM
signal ncs_s : std_ulogic; -- SRAM chip select signal
signal nras_s : std_ulogic; -- DRAM row address stobe signal
signal ncas_s : std_ulogic; -- DRAM column address strobe signal
-- ---------------------------------------------------------------------------------------------------------
begin
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- ASSOCIATION OF INTERNAL SIGNALS (<signal name>_s) TO THE PORT OF THE ENTITY 'emp7160slc84' --
clk_s <= clk; nrst_s <= nrst;
nsend_receive_s <= nsend_receive; baud_rate_select_s <= baud_rate_select; -- DIP-SWITCHES 1-2-3-4
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- connection of port INPUTS of the EPM7160SLC84 EPLD to signals within this architecture -----------
rs232_txd_s <= rs232_txd;
irda_rxda_s <= irda_rxda;
nkey_s <= nkey;
dip_switches_s <= dip_switches;
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- connection of port OUTPUTS of the EPM7160SLC84 EPLD to signals within this architecture ----------
rs232_rxd <= rs232_rxd_s;
irda_txd <= irda_txd_s;
led_array <= led_array_s;
-----------------------------------------------------------------------------------------------------
-- PORT MAP -----------------------------------------------------------------------------------------
epm7160slc84_i: epm7160slc84 port map ( clk=>clk_s, nrst=>nrst_s,
baud_rate_select=>baud_rate_select_s,
nsend_receive=>nsend_receive_s,
rs232_txd=>rs232_txd_s,
rs232_rxd=>rs232_rxd_s,
irda_rxda=>irda_rxda_s,
irda_txd=>irda_txd_s,
nkey=>nkey_s,
dip_switches=>dip_switches_s,
data=>data_s,
address=>address_s,
nwe=>nwe_s,
ncs=>ncs_s,
nras=>nras_s,
ncas=>ncas_s );
noe_s <= '0';
sram_address_s <= "0000" & To_StdLogicVector( address_s );
led_array_s <= To_StdULogicVector( data_s );
sram_i : sram61256 port map ( nwe_s, ncs_s, noe_s, sram_address_s, data_s );
end structure;
-- ---------------------------------------------------------------------------------------------------------
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