-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;
ENTITY internal_flag IS
PORT (d, c, a : IN std_logic; z : OUT std_logic);
END;
ARCHITECTURE behavioral OF internal_flag IS
BEGIN
PROCESS (d, c, a)
VARIABLE flag : std_logic;
BEGIN
IF flag = '1' THEN z <= a AND d;
ELSE z <= '0';
END IF;
IF (c'EVENT AND c = '1') THEN
flag := d;
END IF;
END PROCESS;
END behavioral;
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