gc -product leonardo \ /home/classes/ws97/mrmayer/8051ren/src/al_unit_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/cpu_core_struct.vhd /home/classes/ws97/mrmayer/8051ren/src/dest_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/tmp1_r_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/tmp2_r_spec.vhd \ /home/classes/ws97/mrmayer/8051ren/src/tmp2_r_spec.edf -input_format=VHDL \ -target=xi4 -output_format=EDIF -area -effort=quick \ -edif_timing_file=/home/classes/ws97/mrmayer/8051ren/src/tmp2_r_spec.tim \ -report_full -encoding=OneHot -wire_tree=Worst -nocontrol -vhdl_93 -process=5 \ -chip ------------------------------------------------- Leonardo - V4.1.4 (build 1.108, compiled Oct 10 1997 at 21:09:36) Copyright 1990-1996 Exemplar Logic, Inc. All rights reserved. Checking Security ... Info: setting encoding to OneHot Info: setting process to 5 Info: setting wire_tree to Worst -- -- Welcome to Leonardo -- Run By mrmayer@eceultra20 -- Run Started On Thu Sep 03 00:44:39 CDT 1998 -- -- read -format VHDL {/home/classes/ws97/mrmayer/8051ren/src/al_unit_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/cpu_core_struct.vhd /home/classes/ws97/mrmayer/8051ren/src/dest_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/tmp1_r_spec.vhd /home/classes/ws97/mrmayer/8051ren/src/tmp2_r_spec.vhd} -- Reading file /usr/local/exemplar/data/standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/al_unit_spec.vhd into library work -- Reading file /usr/local/exemplar/data/std_1164.vhd for unit std_logic_1164 -- Loading package std_logic_1164 into library ieee -- Reading file /usr/local/exemplar/data/numeric_std.vhd for unit numeric_std -- Loading package numeric_std into library ieee "numeric_std.vhd",line 878: Warning, range 0 DOWNTO 1 is null range. "numeric_std.vhd",line 879: Warning, range 0 DOWNTO 1 is null range. "numeric_std.vhd",line 3465: Warning, variable value is never used. "numeric_std.vhd",line 3465: Warning, variable value is never assigned a value. -- Reading file cpu_pack.vhd for unit cpu_pack -- Loading package cpu_pack into library mc8051 -- Reading file synth_pack.vhd for unit synth_pack -- Loading package synth_pack into library mc8051 -- Loading entity al_unit into library work -- Loading architecture spec of al_unit into library work "al_unit_spec.vhd",line 97: Warning, signal add_en is never used. "al_unit_spec.vhd",line 97: Warning, signal add_en is never assigned a value. "al_unit_spec.vhd",line 97: Warning, signal sub_en is never used. "al_unit_spec.vhd",line 97: Warning, signal sub_en is never assigned a value. "al_unit_spec.vhd",line 105: Warning, signal tmp2_post is never assigned a value. "al_unit_spec.vhd",line 34: Warning, input use_acc_0 is never used. -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/cpu_core_struct.vhd into library work -- Loading entity cpu_core into library work -- Loading architecture struct of cpu_core into library work -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/dest_spec.vhd into library work -- Loading entity dest into library work -- Loading architecture spec of dest into library work "dest_spec.vhd",line 21: Warning, input acknow is never used. "dest_spec.vhd",line 22: Warning, input alu_done is never used. "dest_spec.vhd",line 23: Warning, input alu_result is never used. "dest_spec.vhd",line 24: Warning, input cpu_rst is never used. "dest_spec.vhd",line 25: Warning, input data_dest is never used. "dest_spec.vhd",line 26: Warning, input dest_cmd is never used. "dest_spec.vhd",line 27: Warning, input int_clk is never used. "dest_spec.vhd",line 28: Warning, input rs is never used. "dest_spec.vhd",line 29: Warning, input two_dests is never used. "dest_spec.vhd",line 30: Warning, output addr_gb is never assigned a value. "dest_spec.vhd",line 31: Warning, output alu_second_result is never assigned a value. "dest_spec.vhd",line 32: Warning, output cpu_done is never assigned a value. "dest_spec.vhd",line 33: Warning, output data_gb is never assigned a value. "dest_spec.vhd",line 34: Warning, output inc_wr_sp is never assigned a value. "dest_spec.vhd",line 35: Warning, output indirect_sel is never assigned a value. "dest_spec.vhd",line 36: Warning, output wr_gb is never assigned a value. -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.vhd into library work -- Loading entity ir_decoder into library work -- Loading architecture spec of ir_decoder into library work "ir_decoder_spec.vhd",line 22: Warning, input cpu_rst is never used. "ir_decoder_spec.vhd",line 24: Warning, input int_clk is never used. "ir_decoder_spec.vhd",line 38: Warning, output use_acc_0 is never assigned a value. -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/tmp1_r_spec.vhd into library work -- Loading entity tmp1_r into library work -- Loading architecture spec of tmp1_r into library work "tmp1_r_spec.vhd",line 29: Warning, output bit_loc is never assigned a value. "tmp1_r_spec.vhd",line 31: Warning, output indirect_sel is never assigned a value. "tmp1_r_spec.vhd",line 35: Warning, output read_pin is never assigned a value. "tmp1_r_spec.vhd",line 38: Warning, inout data_gb is used as input only. -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/tmp2_r_spec.vhd into library work -- Loading entity tmp2_r into library work -- Loading architecture spec of tmp2_r into library work "tmp2_r_spec.vhd",line 32: Warning, output indirect_sel is never assigned a value. "tmp2_r_spec.vhd",line 36: Warning, output read_pin is never assigned a value. -- Compiling root entity tmp2_r(spec) -- Reading target technology xi4 Reading library file `/usr/local/exemplar/lib/xi4.syn`... Library version = 1.46 Delays assume: Process=5 -- Read Module Generators -- Reading module generator description from file /usr/local/exemplar/data/modgen/xi4.vhd -- Reading vhdl file /usr/local/exemplar/data/modgen/xi4.vhd into library OPERATORS -- Modgen File xi4.vhd Version 4.20 -- Pre Optimizing Design .work.tmp2_r.spec -- Resolving Modgen With modgen_select "small" -- Start module generator resolving for design .work.tmp2_r.spec -- optimize -target xi4 -effort quick -chip -area Info, This design has some registers which use both async set & async reset. GSR inferencing in this version does not support such designs. Info, Design is not suitable for GSR processing, skipping. -- Start optimization for design .work.tmp2_r.spec Using default wire table: 4013-5 Warning, asynchronous set & reset on DFF tmp2(7)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(6)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(5)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(4)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(3)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(2)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(1)_$XMPLR replaced by synchronous set & reset. Warning, asynchronous set & reset on DFF tmp2(0)_$XMPLR replaced by synchronous set & reset. Warning, Transformations were required because of constraints in target technology xi4. Warning, Design may show simulation differences because of transformations. Pass Area Delay DFFs PIs POs --CPU-- (FGs) (ns) min:sec 1 34 54 12 29 23 00:02 Info, setting outputs in top level view 'spec' to fast. Using default wire table: 4013-5 -- Start timespec generation for design .work.tmp2_r.spec ******************************************************* Cell: tmp2_r View: spec Library: work ******************************************************* Number of ports : 52 Number of nets : 132 Number of instances : 103 Number of references to this view : 0 Total accumulated area : Number of FG Function Generators : 34 Number of H Function Generators : 2 Number of Packed CLBs : 18 Number of CLB Flip Flops : 12 Number of IBUF : 29 Number of OBUF : 11 Number of OBUFT : 12 -- Writing file /home/classes/ws97/mrmayer/8051ren/src/tmp2_r_spec.edf -- CPU time taken for this run was 16.62 sec -- Run ended On Thu Sep 03 00:44:58 CDT 1998 -- Leonardo run successfully completed. Goodbye !