gc -product leonardo \ /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.vhd \ /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.edf -source=xi4 \ -input_format=VHDL -target=xi4 -output_format=EDIF -area -effort=quick \ -edif_timing_file=/home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.tim \ -report_full -encoding=OneHot -wire_tree=Worst -nocontrol -vhdl_93 -process=5 \ -chip ------------------------------------------------- Leonardo - V4.1.4 (build 1.108, compiled Oct 10 1997 at 21:09:36) Copyright 1990-1996 Exemplar Logic, Inc. All rights reserved. Checking Security ... Info: setting encoding to OneHot Info: setting process to 5 Info: setting wire_tree to Worst -- -- Welcome to Leonardo -- Run By mrmayer@eceultra20 -- Run Started On Thu Sep 03 00:41:55 CDT 1998 -- -- Reading source technology xi4 Reading library file `/usr/local/exemplar/lib/xi4.syn`... Library version = 1.46 Delays assume: Process=5 -- read -format VHDL {/home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.vhd} -- Reading file /usr/local/exemplar/data/standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.vhd into library work -- Reading file /usr/local/exemplar/data/std_1164.vhd for unit std_logic_1164 -- Loading package std_logic_1164 into library ieee -- Reading file /usr/local/exemplar/data/numeric_std.vhd for unit numeric_std -- Loading package numeric_std into library ieee "numeric_std.vhd",line 878: Warning, range 0 DOWNTO 1 is null range. "numeric_std.vhd",line 879: Warning, range 0 DOWNTO 1 is null range. "numeric_std.vhd",line 3465: Warning, variable value is never used. "numeric_std.vhd",line 3465: Warning, variable value is never assigned a value. -- Reading file cpu_pack.vhd for unit cpu_pack -- Loading package cpu_pack into library mc8051 -- Reading file synth_pack.vhd for unit synth_pack -- Loading package synth_pack into library mc8051 -- Loading entity ir_decoder into library work -- Loading architecture spec of ir_decoder into library work "ir_decoder_spec.vhd",line 22: Warning, input cpu_rst is never used. "ir_decoder_spec.vhd",line 24: Warning, input int_clk is never used. "ir_decoder_spec.vhd",line 38: Warning, output use_acc_0 is never assigned a value. -- Compiling root entity ir_decoder(spec) "ir_decoder_spec.vhd",line 56: Warning, cy_int is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 72: Warning, ir_10 should be declared on the sensitivity list of the process. "ir_decoder_spec.vhd",line 131: Warning, ir should be declared on the sensitivity list of the process. "ir_decoder_spec.vhd",line 204: Warning, cy_int should be declared on the sensitivity list of the process. "ir_decoder_spec.vhd",line 642: Warning, alu_second_result should be declared on the sensitivity list of the process. "ir_decoder_spec.vhd",line 34: Warning, set_cy is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 33: Warning, set_ac_ov is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 29: Warning, data_dest is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 39: Warning, use_cy is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 28: Warning, data_alu is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 30: Warning, data_t1 is not always assigned. latches could be needed. "ir_decoder_spec.vhd",line 31: Warning, data_t2 is not always assigned. latches could be needed. -- Read Module Generators -- Reading module generator description from file /usr/local/exemplar/data/modgen/xi4.vhd -- Reading vhdl file /usr/local/exemplar/data/modgen/xi4.vhd into library OPERATORS -- Modgen File xi4.vhd Version 4.20 -- Pre Optimizing Design .work.ir_decoder.spec -- Resolving Modgen With modgen_select "small" -- Start module generator resolving for design .work.ir_decoder.spec -- optimize -target xi4 -effort quick -chip -area Info, GSR inferencing in this version does not work with input latches. Info, Design is not suitable for GSR processing, skipping. -- Start optimization for design .work.ir_decoder.spec Using default wire table: 4013-5 Pass Area Delay DFFs PIs POs --CPU-- (FGs) (ns) min:sec 1 206 78 0 11 33 00:42 Info, setting outputs in top level view 'spec' to fast. Using default wire table: 4013-5 -- Start timespec generation for design .work.ir_decoder.spec ******************************************************* Cell: ir_decoder View: spec Library: work ******************************************************* Number of ports : 46 Number of nets : 357 Number of instances : 346 Number of references to this view : 0 Total accumulated area : Number of FG Function Generators : 219 Number of H Function Generators : 67 Number of Packed CLBs : 108 Number of IBUF : 10 Number of OBUF : 33 Number of IOB Input Flip Flops : 1 -- Writing file /home/classes/ws97/mrmayer/8051ren/src/ir_decoder_spec.edf -- CPU time taken for this run was 76.02 sec -- Run ended On Thu Sep 03 00:43:15 CDT 1998 -- Leonardo run successfully completed. Goodbye !