(edif dest 
 (edifVersion 2 0 0)
 (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status 
  (written 
   (timestamp 1998 09 03 05 37 15)
   (program "Leonardo" (version "V4.1.4"))
   (author "Exemplar Logic Inc")))
 (library work 
  (edifLevel 0)
  (technology (numberDefinition ))
  (cell dest (cellType GENERIC)
   (view spec  (viewType NETLIST)
    (interface 
     (port acknow (direction INPUT))
     (port alu_done (direction INPUT))
     (port (array (rename alu_result "alu_result(7:0)") 8 )(direction INPUT))
     (port cpu_rst (direction INPUT))
     (port (array (rename data_dest "data_dest(2:0)") 3 )(direction INPUT))
     (port (array (rename dest_cmd "dest_cmd(3:0)") 4 )(direction INPUT))
     (port int_clk (direction INPUT))
     (port (array (rename rs "rs(1:0)") 2 )(direction INPUT))
     (port two_dests (direction INPUT))
     (port (array (rename addr_gb "addr_gb(7:0)") 8 )(direction OUTPUT))
     (port alu_second_result (direction OUTPUT))
     (port cpu_done (direction OUTPUT))
     (port (array (rename data_gb "data_gb(7:0)") 8 )(direction OUTPUT))
     (port inc_wr_sp (direction OUTPUT))
     (port indirect_sel (direction OUTPUT))
     (port wr_gb (direction OUTPUT))))))
 (design dest (cellRef dest (libraryRef work ))))

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