gc -product leonardo /home/classes/ws97/mrmayer/8051ren/src/acc_reg_spec.vhd \ /home/classes/ws97/mrmayer/8051ren/src/acc_reg_spec.edf -input_format=VHDL \ -target=xi4 -output_format=EDIF -area -effort=quick \ -edif_timing_file=/home/classes/ws97/mrmayer/8051ren/src/acc_reg_spec.tim \ -report_full -encoding=OneHot -wire_tree=Worst -nocontrol -vhdl_93 -process=5 \ -chip ------------------------------------------------- Leonardo - V4.1.4 (build 1.108, compiled Oct 10 1997 at 21:09:36) Copyright 1990-1996 Exemplar Logic, Inc. All rights reserved. Checking Security ... Info: setting encoding to OneHot Info: setting process to 5 Info: setting wire_tree to Worst -- -- Welcome to Leonardo -- Run By mrmayer@eceultra20 -- Run Started On Thu Sep 03 00:06:06 CDT 1998 -- -- read -format VHDL {/home/classes/ws97/mrmayer/8051ren/src/acc_reg_spec.vhd} -- Reading file /usr/local/exemplar/data/standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file /home/classes/ws97/mrmayer/8051ren/src/acc_reg_spec.vhd into library work -- Reading file /usr/local/exemplar/data/std_1164.vhd for unit std_logic_1164 -- Loading package std_logic_1164 into library ieee -- Reading file /usr/local/exemplar/data/numeric_std.vhd for unit numeric_std -- Loading package numeric_std into library ieee "numeric_std.vhd",line 878: Warning, range 0 DOWNTO 1 is null range. "numeric_std.vhd",line 879: Warning, range 0 DOWNTO 1 is null range. "numeric_std.vhd",line 3465: Warning, variable value is never used. "numeric_std.vhd",line 3465: Warning, variable value is never assigned a value. -- Reading file synth_pack.vhd for unit synth_pack -- Loading package synth_pack into library mc8051 -- Loading entity acc_reg into library work -- Loading architecture spec of acc_reg into library work "acc_reg_spec.vhd",line 22: Warning, input int_clk is never used. -- Compiling root entity acc_reg(spec) "acc_reg_spec.vhd",line 44: Warning, initial value for acc_reg is ignored for synthesis. "acc_reg_spec.vhd",line 44: Warning, acc_reg is not always assigned. latches could be needed. -- Reading target technology xi4 Reading library file `/usr/local/exemplar/lib/xi4.syn`... Library version = 1.46 Delays assume: Process=5 -- Read Module Generators -- Reading module generator description from file /usr/local/exemplar/data/modgen/xi4.vhd -- Reading vhdl file /usr/local/exemplar/data/modgen/xi4.vhd into library OPERATORS -- Modgen File xi4.vhd Version 4.20 -- Pre Optimizing Design .work.acc_reg.spec -- Resolving Modgen With modgen_select "small" -- Start module generator resolving for design .work.acc_reg.spec -- Resolving function eq with module generator modgen_eq_8_small_false from file xi4.vhd -- optimize -target xi4 -effort quick -chip -area -- Start optimization for design .work.acc_reg.spec Using default wire table: 4013-5 Warning, asynchronous reset on DLATCH acc(7)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(6)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(5)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(4)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(3)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(2)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(1)_$XMPLR replaced by combinational logic. Warning, asynchronous reset on DLATCH acc(0)_$XMPLR replaced by combinational logic. Warning, Transformations were required because of constraints in target technology xi4. Warning, Design may show simulation differences because of transformations. Pass Area Delay DFFs PIs POs --CPU-- (FGs) (ns) min:sec 1 17 46 0 12 17 00:01 Info, setting outputs in top level view 'spec' to fast. Using default wire table: 4013-5 -- Start timespec generation for design .work.acc_reg.spec ******************************************************* Cell: acc_reg View: spec Library: work ******************************************************* Number of ports : 30 Number of nets : 94 Number of instances : 88 Number of references to this view : 0 Total accumulated area : Number of FG Function Generators : 25 Number of H Function Generators : 3 Number of Packed CLBs : 9 Number of IBUF : 20 Number of OBUF : 8 Number of OBUFT : 9 -- Writing file /home/classes/ws97/mrmayer/8051ren/src/acc_reg_spec.edf -- CPU time taken for this run was 13.63 sec -- Run ended On Thu Sep 03 00:06:22 CDT 1998 -- Leonardo run successfully completed. Goodbye !