--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.psw.interface
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 19:32:44
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY psw IS
   PORT( 
      ac_out : IN     std_logic ;
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      cy_out : IN     std_logic ;
      indirect_sel : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      ov_out : IN     std_logic ;
      parity : IN     std_logic ;
      rd_gb : IN     std_logic ;
      wr_gb : IN     std_logic ;
      wr_out : IN     std_logic ;
      ac : OUT    std_logic ;
      acknow : OUT    std_logic ;
      cy : OUT    std_logic ;
      ov : OUT    std_logic ;
      rs : OUT    std_logic_vector( 1 DOWNTO 0 )  ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END psw ;
--
-- VHDL Architecture mc8051.psw.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra20.ece.umr.edu)
--          at - 16:43:24 09/19/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
architecture spec of psw is
    SIGNAL psw_reg    : std_logic_vector(7 DOWNTO 0) := "00000000";
    SIGNAL psw_sel    : std_logic;
begin

    -- The psw is sleected by addr D0 and NOT indirect_sel
    psw_sel <= '1' WHEN (addr_gb = "11010000") AND (indirect_sel = '0') ELSE
               '0';

    -- The psw is reset to 0's during reset,
    -- set to the data_gb during a write by wr_gb,
    -- set to the cy_out, ov_out, ac_out when wr_out is '1'
    -- or else left along.
    psw_reg <= "00000000" WHEN int_rst = '1' ELSE
               data_gb   WHEN (wr_gb = '1' AND psw_sel = '1') ELSE
               cy_out & ac_out & psw_reg(5 DOWNTO 3) & ov_out & psw_reg(1 DOWNTO 0)
                         WHEN wr_out = '1' ELSE
               psw_reg(7 DOWNTO 1) & parity;

    -- always drive the following lines:
    rs(1 DOWNTO 0) <= psw_reg(4 DOWNTO 3);
    cy <= psw_reg(7);
    ac <= psw_reg(6);
    ov <= psw_reg(2);

    -- the data_gb  is driven with the acc during a read from acc,
    -- or else left in high impedance.
    data_gb <= psw_reg    WHEN rd_gb = '1' AND psw_sel = '1' ELSE
               "ZZZZZZZZ";
  
    -- The acknowledge is pulled high when the global bus and psw
    -- reg become equal (considered stable) and the psw is selected.
    acknow <= '1' WHEN data_gb = psw_reg AND psw_sel = '1' ELSE
              'Z';
 
end spec;

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