-------------------------------------------------- -- Model : 8051 Behavioral Model, -- VHDL Entity mc8051.program_ctrl.interface -- -- Author : Michael Mayer (mrmayer@computer.org), -- Dr. Hardy J. Pottinger, -- Department of Electrical Engineering -- University of Missouri - Rolla -- -- Created at : 09/22/98 14:04:05 -- LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; LIBRARY mc8051 ; USE mc8051.synth_pack.all; ENTITY program_ctrl IS PORT( cmp_true : IN std_logic ; cycle_states : IN std_logic_vector( 3 DOWNTO 0 ) ; dptr : IN std_logic_vector( 15 DOWNTO 0 ) ; int_clk : IN std_logic ; int_rst : IN std_logic ; pdata : IN std_logic_vector( 7 DOWNTO 0 ) ; rd_pmem1 : IN std_logic ; rd_pmem2 : IN std_logic ; addr_gb : OUT std_logic_vector( 7 DOWNTO 0 ) ; dec_rd_sp : OUT std_logic ; inc_wr_sp : OUT std_logic ; indirect_sel : OUT std_logic ; ir : OUT std_logic_vector( 7 DOWNTO 0 ) ; last_cycle : OUT std_logic ; new_ir : OUT std_logic ; pdat_loc : OUT std_logic_vector( 15 DOWNTO 0 ) ; rd_gb : OUT std_logic ; wr_gb : OUT std_logic ; acknow : INOUT std_logic ; data_gb : INOUT std_logic_vector( 7 DOWNTO 0 ) ); -- Declarations END program_ctrl ; -- -- VHDL Architecture mc8051.program_ctrl.struct -- -- Created: -- by - mrmayer.UNKNOWN (eceultra3.ece.umr.edu) -- at - 14:04:08 09/22/98 -- -- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18) -- LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; LIBRARY mc8051 ; USE mc8051.synth_pack.all; LIBRARY mc8051; ARCHITECTURE struct OF program_ctrl IS -- Architecture declarations -- Internal signal declarations SIGNAL call_addr : std_logic_vector( 15 DOWNTO 0 ) ; SIGNAL force_lcall : std_logic; SIGNAL new_pc : std_logic_vector( 15 DOWNTO 0 ) ; SIGNAL pc : std_logic_vector( 15 DOWNTO 0 ) ; SIGNAL pmem1 : std_logic_vector( 7 DOWNTO 0 ) ; SIGNAL pmem2 : std_logic_vector( 7 DOWNTO 0 ) ; SIGNAL wr_pc : std_logic; -- Implicit buffer signal declarations SIGNAL ir_internal : std_logic_vector( 7 DOWNTO 0 ) ; SIGNAL new_ir_internal : std_logic; SIGNAL last_cycle_internal : std_logic; -- Component Declarations COMPONENT int_hand PORT ( int_clk : IN std_logic; int_rst : IN std_logic; last_cycle : IN std_logic; call_addr : OUT std_logic_vector( 15 DOWNTO 0 ); force_lcall : OUT std_logic ); END COMPONENT; COMPONENT pc_chg PORT ( cmp_true : IN std_logic; cycle_states : IN std_logic_vector( 3 DOWNTO 0 ); dptr : IN std_logic_vector( 15 DOWNTO 0 ); int_clk : IN std_logic; int_rst : IN std_logic; ir : IN std_logic_vector( 7 DOWNTO 0 ); last_cycle : IN std_logic; new_ir : IN std_logic; pc : IN std_logic_vector( 15 DOWNTO 0 ); pmem1 : IN std_logic_vector( 7 DOWNTO 0 ); pmem2 : IN std_logic_vector( 7 DOWNTO 0 ); addr_gb : OUT std_logic_vector( 7 DOWNTO 0 ); dec_rd_sp : OUT std_logic; inc_wr_sp : OUT std_logic; indirect_sel : OUT std_logic; new_pc : OUT std_logic_vector( 15 DOWNTO 0 ); rd_gb : OUT std_logic; wr_gb : OUT std_logic; wr_pc : OUT std_logic; acknow : INOUT std_logic; data_gb : INOUT std_logic_vector( 7 DOWNTO 0 ) ); END COMPONENT; COMPONENT pc_inc PORT ( cycle_states : IN std_logic_vector( 3 DOWNTO 0 ); force_lcall : IN std_logic; int_clk : IN std_logic; int_rst : IN std_logic; ir : IN std_logic_vector( 7 DOWNTO 0 ); new_ir : IN std_logic; pc : IN std_logic_vector( 15 DOWNTO 0 ); last_cycle : OUT std_logic; pdat_loc : OUT std_logic_vector( 15 DOWNTO 0 ); wr_pc : OUT std_logic; new_pc : INOUT std_logic_vector( 15 DOWNTO 0 ) ); END COMPONENT; COMPONENT pmem_reg PORT ( call_addr : IN std_logic_vector( 15 DOWNTO 0 ); cycle_states : IN std_logic_vector( 3 DOWNTO 0 ); force_lcall : IN std_logic; int_clk : IN std_logic; int_rst : IN std_logic; last_cycle : IN std_logic; new_pc : IN std_logic_vector( 15 DOWNTO 0 ); pdata : IN std_logic_vector( 7 DOWNTO 0 ); rd_pmem1 : IN std_logic; rd_pmem2 : IN std_logic; wr_pc : IN std_logic; acknow : OUT std_logic; data_gb : OUT std_logic_vector( 7 DOWNTO 0 ); ir : OUT std_logic_vector( 7 DOWNTO 0 ); new_ir : OUT std_logic; pc : OUT std_logic_vector( 15 DOWNTO 0 ); pmem1 : OUT std_logic_vector( 7 DOWNTO 0 ); pmem2 : OUT std_logic_vector( 7 DOWNTO 0 ) ); END COMPONENT; -- Optional embedded configurations --synopsys translate_off FOR ALL : int_hand USE ENTITY mc8051.int_hand; FOR ALL : pc_chg USE ENTITY mc8051.pc_chg; FOR ALL : pc_inc USE ENTITY mc8051.pc_inc; FOR ALL : pmem_reg USE ENTITY mc8051.pmem_reg; --synopsys translate_on BEGIN -- Instance port mappings. I3 : int_hand PORT MAP ( int_clk => int_clk, int_rst => int_rst, last_cycle => last_cycle_internal, call_addr => call_addr(15 downto 0), force_lcall => force_lcall ); I0 : pc_chg PORT MAP ( cmp_true => cmp_true, cycle_states => cycle_states(3 downto 0), dptr => dptr(15 downto 0), int_clk => int_clk, int_rst => int_rst, ir => ir_internal(7 downto 0), last_cycle => last_cycle_internal, new_ir => new_ir_internal, pc => pc(15 downto 0), pmem1 => pmem1(7 downto 0), pmem2 => pmem2(7 downto 0), addr_gb => addr_gb(7 downto 0), dec_rd_sp => dec_rd_sp, inc_wr_sp => inc_wr_sp, indirect_sel => indirect_sel, new_pc => new_pc(15 downto 0), rd_gb => rd_gb, wr_gb => wr_gb, wr_pc => wr_pc, acknow => acknow, data_gb => data_gb(7 downto 0) ); I1 : pc_inc PORT MAP ( cycle_states => cycle_states(3 downto 0), force_lcall => force_lcall, int_clk => int_clk, int_rst => int_rst, ir => ir_internal(7 downto 0), new_ir => new_ir_internal, pc => pc(15 downto 0), last_cycle => last_cycle_internal, pdat_loc => pdat_loc(15 downto 0), wr_pc => wr_pc, new_pc => new_pc(15 downto 0) ); I2 : pmem_reg PORT MAP ( call_addr => call_addr(15 downto 0), cycle_states => cycle_states(3 downto 0), force_lcall => force_lcall, int_clk => int_clk, int_rst => int_rst, last_cycle => last_cycle_internal, new_pc => new_pc(15 downto 0), pdata => pdata(7 downto 0), rd_pmem1 => rd_pmem1, rd_pmem2 => rd_pmem2, wr_pc => wr_pc, acknow => acknow, data_gb => data_gb(7 downto 0), ir => ir_internal(7 downto 0), new_ir => new_ir_internal, pc => pc(15 downto 0), pmem1 => pmem1(7 downto 0), pmem2 => pmem2(7 downto 0) ); -- Implicit buffered output assignments ir <= ir_internal; new_ir <= new_ir_internal; last_cycle <= last_cycle_internal; END struct;