--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.pmem_reg.interface
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 19:39:48
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY pmem_reg IS
   PORT( 
      call_addr : IN     std_logic_vector( 15 DOWNTO 0 )  ;
      cycle_states : IN     std_logic_vector( 3 DOWNTO 0 )  ;
      force_lcall : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      last_cycle : IN     std_logic ;
      new_pc : IN     std_logic_vector( 15 DOWNTO 0 )  ;
      pdata : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      rd_pmem1 : IN     std_logic ;
      rd_pmem2 : IN     std_logic ;
      wr_pc : IN     std_logic ;
      acknow : OUT    std_logic ;
      data_gb : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      ir : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      new_ir : OUT    std_logic ;
      pc : OUT    std_logic_vector( 15 DOWNTO 0 )  ;
      pmem1 : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      pmem2 : OUT    std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END pmem_reg ;
--
-- VHDL Architecture mc8051.pmem_reg.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra7.ece.umr.edu)
--          at - 12:37:22 08/29/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.0 (Build 110)
--
architecture spec of pmem_reg is

   SIGNAL pc_reg     : std_logic_vector (15 DOWNTO 0);
   SIGNAL pmem1_reg, pmem2_reg, ir_reg : std_logic_vector (7 DOWNTO 0); 
   SIGNAL pmem1_gd,  pmem2_gd,  ir_gd  : std_logic;
   SIGNAL new_ir1   : std_logic;

BEGIN

   -- latch for pc
   pc_reg <= (OTHERS => '0') WHEN int_rst = '1' ELSE
             new_pc WHEN rising_edge(int_clk) AND wr_pc = '1' ELSE
             pc_reg;
   pc <= pc_reg;

   -- get new ir using flip flops
   ir_ff : PROCESS (int_clk,int_rst ) IS
   BEGIN
      -- In a reset situation, create a NOP until s6p2.
    IF int_rst = '1' THEN
         ir_gd <= '1';
         ir_reg <= "00000000";
         new_ir <= '0';
    ELSIF rising_edge(int_clk) THEN
      IF last_cycle = '1' AND cycle_states = s6p2 THEN
         ir_gd <= '0';
      END IF;
      IF ir_gd = '0' AND cycle_states = s1p1 THEN
         IF force_lcall = '1' THEN
            ir_reg <= "00010010";  -- LCALL forced from interrupt
         ELSE
            ir_reg <= pdata;
         END IF;
         ir_gd <= '1';
         new_ir1 <= '1';
      ELSE
         new_ir <= '0';
         new_ir1 <= '0';
      END IF;
    ELSIF falling_edge(int_clk) THEN
      IF new_ir1 = '1' THEN
         new_ir <= '1';
      END IF;
    END IF;
   END PROCESS ir_ff;
   ir <= ir_reg;

   -- get first byte of program memory
   pmem1_ff : PROCESS (int_clk ) IS
   BEGIN
    IF rising_edge(int_clk) THEN
      IF last_cycle = '1' AND cycle_states = s6p2 THEN
         pmem1_gd <= '0';
      END IF;
      IF pmem1_gd = '0' AND cycle_states = s4p1 THEN
         IF force_lcall = '1' THEN
            pmem1_reg <= call_addr(15 DOWNTO 8);  -- LCALL forced from interrupt
         ELSE
            pmem1_reg <= pdata;
         END IF;
         pmem1_gd <= '1';
      END IF;
    END IF;
   END PROCESS pmem1_ff;
   pmem1 <= pmem1_reg;

   -- get second byte of program memory
   pmem2_ff : PROCESS (int_clk ) IS
   BEGIN
    IF rising_edge(int_clk) THEN
      IF last_cycle = '1' AND cycle_states = s6p2 THEN
         pmem2_gd <= '0';
      END IF;
      IF ir_gd = '1' AND pmem2_gd = '0' AND cycle_states = s1p1 THEN
         IF force_lcall = '1' THEN
            pmem2_reg <= call_addr(7 DOWNTO 0);  -- LCALL forced from interrupt
         ELSE
            pmem2_reg <= pdata;
         END IF;
         pmem2_gd <= '1';
      END IF;
    END IF;
   END PROCESS pmem2_ff;
   pmem2 <= pmem2_reg;
         
   -- handle the data global bus
   data_gb <= pmem1_reg WHEN (rd_pmem1 = '1' AND pmem1_gd = '1') ELSE
              pmem2_reg WHEN (rd_pmem2 = '1' AND pmem2_gd = '1') ELSE
              (OTHERS => 'Z');
   acknow  <= '1' WHEN (rd_pmem1 = '1' AND pmem1_gd = '1') OR
                       (rd_pmem2 = '1' AND pmem2_gd = '1') ELSE
              'Z';

END ARCHITECTURE spec;

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