--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.p1_drv.interface
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 19:32:39
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY p1_drv IS
   PORT( 
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      indirect_sel : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      latch_pins : IN     std_logic ;
      rd_gb : IN     std_logic ;
      read_latch : IN     std_logic ;
      wr_gb : IN     std_logic ;
      acknow : OUT    std_logic ;
      P1 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END p1_drv ;
--
-- VHDL Architecture mc8051.p1_drv.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra20.ece.umr.edu)
--          at - 19:51:01 09/19/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
architecture spec of p1_drv is
    SIGNAL  p1_reg   : bvec := "00000000";
    SIGNAL  p1_sel   : std_logic;
 
begin
    -- The p1 is selected by addr 90 and NOT indirect_sel
    p1_sel <= '1' WHEN (addr_gb = "10010000") AND (indirect_sel = '0') ELSE
              '0';
 
    -- The p1 is reset to 1's during reset,
    -- set to the data_gb during a write to p1, or else left alone.
    p1_reg <= "11111111" WHEN int_rst = '1' ELSE                 -- reset
               unsigned(data_gb)   WHEN (wr_gb = '1' AND p1_sel = '1') ELSE -- async
               p1_reg;
 
    p1 <= std_logic_vector(to_high_imped(p1_reg));
 
    -- The data_gb is driven with the p1_ref during a read from p1_reg,
    -- or else left in high impedance.
    data_gb <= to_x01(p1) WHEN rd_gb = '1' AND p1_sel = '1' AND read_latch = '0' ELSE
               std_logic_vector(p1_reg)    WHEN rd_gb = '1' AND p1_sel = '1' AND read_latch = '1' ELSE
               "ZZZZZZZZ";
 
    -- The acknowledge is pulled high when the global bus and p1
    -- reg become equal (considered stable) and the p1 is selected.
    acknow <= '1' WHEN data_gb = std_logic_vector(p1_reg) AND p1_sel = '1' ELSE
              'Z';
 

end spec;

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