LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; LIBRARY mc8051 ; USE mc8051.cpu_pack.all; USE mc8051.synth_pack.all; ENTITY tmp_regs IS PORT( acc : IN std_logic_vector( 7 DOWNTO 0 ) ; acknow : IN std_logic ; alu_result : IN std_logic_vector( 7 DOWNTO 0 ) ; cpu_rst : IN std_logic ; data_dest : IN std_logic_vector( 2 DOWNTO 0 ) ; data_t1 : IN std_logic_vector( 2 DOWNTO 0 ) ; data_t2 : IN std_logic_vector( 2 DOWNTO 0 ) ; dest_cmd : IN std_logic_vector( 3 DOWNTO 0 ) ; int_clk : IN std_logic ; new_ir : IN std_logic ; rs : IN std_logic_vector( 1 DOWNTO 0 ) ; t1_cmd : IN std_logic_vector( 3 DOWNTO 0 ) ; t2_cmd : IN std_logic_vector( 3 DOWNTO 0 ) ; two_dests : IN std_logic ; addr_gb : OUT std_logic_vector( 7 DOWNTO 0 ) ; alu_second_result : OUT std_logic ; bit_loc : OUT std_logic_vector( 2 DOWNTO 0 ) ; cpu_done : OUT std_logic ; dec_rd_sp : OUT std_logic ; inc_wr_sp : OUT std_logic ; indirect_sel : OUT std_logic ; rd_gb : OUT std_logic ; rd_pmem1 : OUT std_logic ; rd_pmem2 : OUT std_logic ; tmp1 : OUT std_logic_vector( 7 DOWNTO 0 ) ; tmp1_done : OUT std_logic ; tmp2 : OUT std_logic_vector( 7 DOWNTO 0 ) ; wr_acc : OUT std_logic ; wr_gb : OUT std_logic ; wr_out : OUT std_logic ; data_gb : INOUT std_logic_vector( 7 DOWNTO 0 ) ); -- Declarations END tmp_regs ;