LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; package synth_pack is SUBTYPE bvec IS UNSIGNED(7 DOWNTO 0); SUBTYPE wvec IS UNSIGNED(15 DOWNTO 0); -- The following type is used to declare if direct or indirect memory -- access is being used and, hence, which segment of upper memory -- is to be used. TYPE access_type IS (direct, indirect); -- The following type is used to break up the machine cycle -- into 6 states, with 2 pulses for each state CONSTANT s1p1 : std_logic_vector(3 DOWNTO 0) := "0100"; CONSTANT s1p2 : std_logic_vector(3 DOWNTO 0) := "0101"; CONSTANT s2p1 : std_logic_vector(3 DOWNTO 0) := "0110"; CONSTANT s2p2 : std_logic_vector(3 DOWNTO 0) := "0111"; CONSTANT s3p1 : std_logic_vector(3 DOWNTO 0) := "1000"; CONSTANT s3p2 : std_logic_vector(3 DOWNTO 0) := "1001"; CONSTANT s4p1 : std_logic_vector(3 DOWNTO 0) := "1010"; CONSTANT s4p2 : std_logic_vector(3 DOWNTO 0) := "1011"; CONSTANT s5p1 : std_logic_vector(3 DOWNTO 0) := "1100"; CONSTANT s5p2 : std_logic_vector(3 DOWNTO 0) := "1101"; CONSTANT s6p1 : std_logic_vector(3 DOWNTO 0) := "1110"; CONSTANT s6p2 : std_logic_vector(3 DOWNTO 0) := "1111"; FUNCTION to_high_imped(arg : bvec) RETURN bvec; end synth_pack;