LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY inter_ctrl IS
   PORT( 
      P0 : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      acknow : IN     std_logic ;
      cycle_states : IN     std_logic_vector( 3 DOWNTO 0 )  ;
      dptr : IN     std_logic_vector( 15 DOWNTO 0 )  ;
      ea_n : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      ir : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      last_cycle : IN     std_logic ;
      pdat_loc : IN     std_logic_vector( 15 DOWNTO 0 )  ;
      rom_data : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      rs : IN     std_logic_vector( 1 DOWNTO 0 )  ;
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      ale : OUT    std_logic ;
      indirect_sel : OUT    std_logic ;
      p0_addr : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      p0_ctrl : OUT    std_logic ;
      p2_addr : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      p2_ctrl : OUT    std_logic ;
      pdata : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      psen_n : OUT    std_logic ;
      rd_gb : OUT    std_logic ;
      rd_n : OUT    std_logic ;
      rd_n_ctrl : OUT    std_logic ;
      rom_rd_n : OUT    std_logic ;
      wr_gb : OUT    std_logic ;
      wr_n : OUT    std_logic ;
      wr_n_ctrl : OUT    std_logic ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END inter_ctrl ;

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