ENTITY acc_reg IS PORT( addr_gb : IN std_logic_vector( 7 DOWNTO 0 ) ; indirect_sel : IN std_logic ; int_clk : IN std_logic ; int_rst : IN std_logic ; rd_gb : IN std_logic ; wr_acc : IN std_logic ; wr_gb : IN std_logic ; acc : OUT std_logic_vector( 7 DOWNTO 0 ) ; acknow : OUT std_logic ; parity : OUT std_logic ; data_gb : INOUT std_logic_vector( 7 DOWNTO 0 ) ); -- Declarations END acc_reg ;