--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.acc_reg.interface
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 19:32:43
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY acc_reg IS
   PORT( 
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      indirect_sel : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      rd_gb : IN     std_logic ;
      wr_acc : IN     std_logic ;
      wr_gb : IN     std_logic ;
      acc : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      acknow : OUT    std_logic ;
      parity : OUT    std_logic ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END acc_reg ;
--
-- VHDL Architecture mc8051.acc_reg.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eeultra20.ee.umr.edu)
--          at - 12:06:56 03/25/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.0 (Build 110)
--
architecture spec of acc_reg is
    SIGNAL  acc_reg   : std_logic_vector (7 DOWNTO 0) := "00000000";
    SIGNAL  acc_sel   : std_logic;
begin
    -- The acc is selected by addr E0 and NOT indirect_sel
    acc_sel <= '1' WHEN (addr_gb = "11100000") AND (indirect_sel = '0') ELSE
               '0';     
    -- The acc is reset to 0's during reset, 
    -- set to the data_gb during a write to acc, or else left alone.
    acc_reg <= "00000000" WHEN int_rst = '1' ELSE                 -- reset
               data_gb    WHEN (wr_gb = '1' AND acc_sel = '1')
                               OR (wr_acc = '1')  ELSE -- async
               acc_reg;

    -- always drive acc_reg to acc line
    acc <= acc_reg;

    -- The data_gb is driven with the acc during a read from acc, 
    -- or else left in high impedance.
    data_gb <= acc_reg    WHEN rd_gb = '1' AND acc_sel = '1' ELSE
               "ZZZZZZZZ"; 
   
    -- The acknowledge is pulled high when the global bus and acc
    -- reg become equal (considered stable) and the acc is selected.
    acknow <= '1' WHEN data_gb = acc_reg AND acc_sel = '1' ELSE
              'Z';

    parity <= (acc_reg(7) XOR acc_reg(6)) XOR (acc_reg(5) XOR acc_reg(4)) XOR
              (acc_reg(3) XOR acc_reg(2)) XOR (acc_reg(1) XOR acc_reg(0));
end spec;

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