LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE std.textio.ALL;
LIBRARY mc8051;
USE mc8051.ALL;

ENTITY tbr IS
END ENTITY tbr;

ARCHITECTURE a1 OF tbr IS

   COMPONENT mc8051 IS
       PORT (
            ea_n : IN     std_logic ;
            rst : IN     std_logic ;
            xtal1 : IN     std_logic ;
            ale : OUT    std_logic ;
            psen_n : OUT    std_logic ;
            xtal2 : OUT    std_logic ;
            P0 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
            P1 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
            P2 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
            P3 : INOUT  std_logic_vector( 7 DOWNTO 0 )
       );
    END COMPONENT mc8051;

    SIGNAL p0, p1, p2, p3 : std_logic_vector(7 DOWNTO 0);
    SIGNAL clock      : std_logic;

    FOR ALL : mc8051 USE ENTITY mc8051.mc8051;


BEGIN

   ext_int : PROCESS IS
   BEGIN
      WAIT FOR 20 ms;
      P3(2) <= '0';
      WAIT FOR 1 us;
      P3(2) <= '1';
   END PROCESS ext_int;

   clockgen : PROCESS IS 
   BEGIN
       -- 11.059 MHz clock, or 90.4 ns period
       -- = 90400 ps
       clock <= '0';
       WAIT FOR 45200 ps;
       clock <= '1';
       WAIT FOR 45200 ps;
   END PROCESS clockgen;

   uut : mc8051
       PORT MAP (
           P0 => p0,
           P1 => p1,
           P2 => p2,
           P3 => p3,
           rst => '0',
           xtal1 => clock,
           ea_n => '1'
       );

   pulse_modulate : PROCESS IS
       CONSTANT period      : TIME := 100 us;
       CONSTANT duty_cycle1 : REAL := 0.7;
       CONSTANT duty_cycle2 : REAL := 0.3;
   BEGIN
       p1(0) <= '1';
       WAIT FOR period * duty_cycle1;
       p1(0) <= '0';
       WAIT FOR period * (1.0 - duty_cycle1);
       p1(0) <= '1';
       WAIT FOR period * duty_cycle2;
       p1(0) <= '0';
       WAIT FOR period * (1.0 - duty_cycle2);
       WAIT;
   END PROCESS pulse_modulate;

END;
        

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