LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY pwm IS
  PORT(
     output : OUT std_logic
   );
END ENTITY pwm;

ARCHITECTURE spec OF pwm IS
BEGIN
       pulse_modulate : PROCESS IS
       CONSTANT period      : TIME := 60 us;
       CONSTANT duty_cycle1 : REAL := 0.7;
       CONSTANT duty_cycle2 : REAL := 0.3;
   BEGIN
       output <= '1';
       WAIT FOR period * duty_cycle1;
       output <= '0';
       WAIT FOR period * (1.0 - duty_cycle1);
       output <= '1';
       WAIT FOR period * duty_cycle2;
       output <= '0';
       WAIT FOR period * (1.0 - duty_cycle2);
   END PROCESS pulse_modulate;

END spec;

<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br />&nbsp;</div>